Reproducible simulation of multi-threaded workloads for architecture design exploration

As multiprocessors become mainstream, techniques to ad-dress efficient simulation of multi-threaded workloads are needed. Multi-threaded simulation presents a new challenge: non-determinism across simulations for different architecture configurations. If the execution paths between two simulation runs of the same benchmark with the same input are too different, the simulation results cannot be used to compare the configurations. In this paper we focus on a simulation technique to efficiently collect simulation checkpoints for multi-threaded workloads, and to compare simulation runs addressing this non-determinism problem. We focus on user-level simulation of multi-threaded workloads for multiprocessor architectures. We present an approach, based on binary instrumentation, to collect checkpoints for simulation. Our checkpoints allow reproducible execution of the samples across different ar-chitecture configurations by controlling the sources of non-determinism during simulation. This results in stalls that would not naturally occur in execution. We propose techniques that allow us to accurately compare performance across architec-ture configurations in the presence of these stalls. I