Reordering Algorithm for Minimizing Test Power in VLSI Circuits

Abstract — Power consumption has become a crucial concern in Built In Self Test (BIST) due to the switching activity in the circuit under test(CUT). In this paper we present a novel method which aims at minimizing the total power consumption during testing. This is achieved by minimizing the switching activity in the circuit by reducing the Hamming Distance between successive test vectors. In this method the test vectors are reordered for minimum total hamming distance and the same vector set is used for testing. Experimental results with ISCAS benchmark circuits show that the switching activity can be reduced up to 21 % in comparison with conventional ATPG Algorithms like DEFGEN. The Switching activity is reduced significantly when compared with existing methods