Advances in panel glass packaging of mems and sensors for low stress and near hermetic reliability

MEMS based sensing is gaining widespread adoption in consumer electronics as well as the next generation Internet of Things (IoT) market. Such applications serve as primary drivers towards miniaturization for increased component density, multi-chip integration, lower cost and better reliability. Traditional approaches like System-on-Chip (SoC) and System on Board (SoB) are not ideal to address these challenges and there is a need to find solutions at package level, through heterogeneous package integration (HPI). However, existing MEMS packaging techniques like laminate/ceramic substrate packaging and silicon wafer level packaging face challenges like standardization, heterogeneous package integration and form factor miniaturization. Besides, application specific packages take up the largest fraction of the total manufacturing cost. Therefore, advanced packaging of MEMS sensors for HPI plays a critical role in the short and long run towards the SOP vision. This dissertation demonstrates a low stress, reliable, near-hermetic ultra-thin glass cavity MEMS packages as a solution that combines the advantages of LTCC/laminate substrates and silicon wafer level packaging while also addressing their limitations. These glass based cavity packages can be scaled down to 2x smaller form factors (<500μm) and are fabricated out of large panel fabrication processes thereby addressing the cost and form factor requirements of MEMS packaging. Flexible cavity design, advances in through-glass via technologies and dimensional stability of thin glass also enable die stacking and 3D assembly for sensor-processor integration towards sensor fusion. The following building block technologies were explored: (a) reliable cavity formation in thin glass panels (b) low stress glass-glass bonding, and (c) high throughput, fully filled through-package-via metallization in glass. Three main technical challenges were overcome to realize the objectives: (a) glass cracking, side wall taper, side wall roughness and defects, (b) interfacial voids at glass-polymer-glass interface and (c) electrical opens and high frequency performance of copper paste filled through-package-vias in glass.M.S

High Temperature Characterization of Ge2Sb2Te5Thin Films for Phase Change Memory Applications

The recent proliferation of portable communication devices or data storage equipment is strongly related to the development of memory technology. Non-volatile semiconductor solid-state memories are needed for high-capacity storage media, high-speed operation and low power consumption, with stringent requirements of retention and endurance. Phase change memory (PCM) is currently seen as one of the most promising candidates for a future storage-class memory with the potential to be close to dynamic random-access memory (DRAM) in speed but with much longer retention times and as dense as flash memory. PCM devices utilize chalcogenide materials (most commonly Ge2Sb2Te5 or GST) that can be switched rapidly and reversibly between amorphous and crystalline phases with orders of magnitude difference in electrical resistivity. Since PCM devices operate at elevated (current-induced) temperatures and are significantly impacted by thermoelectric effects it is very important to determine the high temperature material properties of GST. Resistivity, carrier mobility, and carrier concentration in semiconducting materials are three key parameters indispensable for device modeling. In this work two measurement setups for high temperature thin film characterizations were developed, a Seebeck setup and a Hall setup. The Seebeck coefficient measurement setup is fully automated and uses resistive and inductive heaters to control the temperature gradient and can reach temperatures up to ~650 °C. The Hall measurement setup, developed based on the van der Paw method for characterization of semiconducting thin films, can measure thin film samples of a wide resistivity range from room temperature to ~500 °C. The resistivity, carrier concentration, and Hall carrier mobility are calculated from I-V measurements and the constant magnetic field applied in ‘up’ and ‘down’ directions. Measurement results on GST thin films with different thicknesses revealed interesting correlations between S-T and ρ-T characteristics and showed that GST behaves as a unipolar p-type semiconducting material from room temperature up to melting. The thermoelectric properties of the GST films were also correlated to the average grain sizes obtained from in-situ XRD measurements during crystallization. These studies show that the activation energy of carriers in mixed phase amorphous-fcc GST is a linear function of the Peltier coefficient. From these results and the ρ-T characteristics, the expected Seebeck coefficient of single crystal fcc GST is obtained. Using the experimental results for resistivity and Seebeck coefficient, together with a phase separation model, the temperature-dependent thermal conductivity of the mixed phase GST is extracted