Regular layout generation of logically optimized datapaths

The inherent distortion of the structural regularity of VLSI data-paths after logic optimization has until now precluded dense regu-lar layouts of optimized datapaths despite their implicit regularity. This paper presents a methodology enabling utilization of datapath regularity for dense layout even after extensive logic optimization. A structural netlist analysis extracts regularity from the initial un-optimized netlist which serves as a partial relative regular preplace-ment. After each customary iteration of placement, backannota-tion and logic optimization, functional correspondences between the optimized and the original netlists are identified by a logic correspondence extractor. The functional and structural analyses results are then merged yielding a regular preplacement for the logically optimized design. 1

Regular layout generation of logically optimized datapaths

The inherent distortion of the structural regularity of VLSI data-paths after logic optimization has until now precluded dense regu-lar layouts of optimized datapaths despite their implicit regularity. This paper presents a methodology enabling utilization of datapath regularity for dense layout even after extensive logic optimization. A structural netlist analysis extracts regularity from the initial un-optimized netlist which serves as a partial relative regular preplace-ment. After each customary iteration of placement, backannota-tion and logic optimization, functional correspondences between the optimized and the original netlists are identified by a logic correspondence extractor. The functional and structural analyses results are then merged yielding a regular preplacement for the logically optimized design. 1