Register Allocation in Hyper-block for EPIC Processors

A hyper-block represents a linear sequence of predicated instructions with a single entry and multiple exit points. To exploit the high level of Instruction Level Parallelism(ILP) in EPIC architectures, hyper-blocks are often used as the unit of program presentation. In this paper, we study the impact of predication and the hyper-block representation in the register allocation phases. Our contribution is as follows. We show that by constructing live ranges in a fine-grained manner the number of interferences can be reduced, and hence this allows both faster compilation and runtime execution. We compare the effect of live range granularity in both hyper-block and conventional basic block. We show that predicate-aware liveness analysis can be used to obtain accurate interference graphs and to reduce false register pressure. Similarly, we demonstrate that a predicate-aware priority function can give a better register allocation performance over a predicate-insensitive one. We also identif..