Random Pattern Testing for Sequential Circuits Revisited

Random pattern testing methods are known to result in poor fault coverage for most sequential circuits unless costly circuit modification methods are employed. In this paper we propose a novel approach to improve the random pattern testability of sequential circuits. We introduce the concept of holding signals at primary inputs and scan flip-flops for a certain length of time instead of applying a new random vector at each clock cycle. When a random vector is held at the primary inputs of the circuit under test or at the scan flip-flops, the system clock is applied and the primary outputs of the circuit are observed. The number of clock cycles, k, for which each random input is held at a fixed value, before applying the next random vector, is determined by using testability analysis or a test pattern generator for a very small number of lines or faults in the circuit. The lines or faults that are analyzed are the primary inputs to flip-flops. The information obtained from the testabili..