Product assurance technology for custom LSI/VLSI electronics

The technology for obtaining custom integrated circuits from CMOS-bulk silicon foundries using a universal set of layout rules is presented. The technical efforts were guided by the requirement to develop a 3 micron CMOS test chip for the Combined Release and Radiation Effects Satellite (CRRES). This chip contains both analog and digital circuits. The development employed all the elements required to obtain custom circuits from silicon foundries, including circuit design, foundry interfacing, circuit test, and circuit qualification

On the test of single via related defects in digital VLSI designs

Vias are critical for digital circuit manufacturing, as they represent a common defect location, and a general DfM rule suggests replicating every instance for redundancy. When this is not achievable, a mandatory requirement is that the remaining single vias must be tested. We propose an automated method for generating tests and accurately evaluating test coverage of such defects, ready for use in any digital implementation flow and for integration within EDA tools, and also providing a useful quality metric. A prototype tool implementation and experimental results for an industrial case study are presented

Transition Faults and Transition Path Delay Faults: Test Generation, Path Selection, and Built-In Generation of Functional Broadside Tests

As the clock frequency and complexity of digital integrated circuits increase rapidly, delay testing is indispensable to guarantee the correct timing behavior of the circuits. In this dissertation, we describe methods developed for three aspects of delay testing in scan-based circuits: test generation, path selection and built-in test generation. We first describe a deterministic broadside test generation procedure for a path delay fault model named the transition path delay fault model, which captures both large and small delay defects. Under this fault model, a path delay fault is detected only if all the individual transition faults along the path are detected by the same test. To reduce the complexity of test generation, sub-procedures with low complexity are applied before a complete branch-and-bound procedure. Next, we describe a method based on static timing analysis to select critical paths for test generation. Logic conditions that are necessary for detecting a path delay fault are considered to refine the accuracy of static timing analysis, using input necessary assignments. Input necessary assignments are input values that must be assigned to detect a fault. The method calculates more accurate path delays, selects paths that are critical during test application, and identifies undetectable path delay faults. These two methods are applicable to off-line test generation. For large circuits with high complexity and frequency, built-in test generation is a cost-effective method for delay testing. For a circuit that is embedded in a larger design, we developed a method for built-in generation of functional broadside tests to avoid excessive power dissipation during test application and the overtesting of delay faults, taking the functional constraints on the primary input sequences of the circuit into consideration. Functional broadside tests are scan-based two-pattern tests for delay faults that create functional operation conditions during test application. To avoid the potential fault coverage loss due to the exclusive use of functional broadside tests, we also developed an optional DFT method based on state holding to improve fault coverage. High delay fault coverage can be achieved by the developed method for benchmark circuits using simple hardware

System configuration, fault detection, location, isolation and restoration: a review on LVDC Microgrid protections

Low voltage direct current (LVDC) distribution has gained the significant interest of research due to the advancements in power conversion technologies. However, the use of converters has given rise to several technical issues regarding their protections and controls of such devices under faulty conditions. Post-fault behaviour of converter-fed LVDC system involves both active converter control and passive circuit transient of similar time scale, which makes the protection for LVDC distribution significantly different and more challenging than low voltage AC. These protection and operational issues have handicapped the practical applications of DC distribution. This paper presents state-of-the-art protection schemes developed for DC Microgrids. With a close look at practical limitations such as the dependency on modelling accuracy, requirement on communications and so forth, a comprehensive evaluation is carried out on those system approaches in terms of system configurations， fault detection, location, isolation and restoration

Design of a fault tolerant airborne digital computer. Volume 2: Computational requirements and technology

This final report summarizes the work on the design of a fault tolerant digital computer for aircraft. Volume 2 is composed of two parts. Part 1 is concerned with the computational requirements associated with an advanced commercial aircraft. Part 2 reviews the technology that will be available for the implementation of the computer in the 1975-1985 period. With regard to the computation task 26 computations have been categorized according to computational load, memory requirements, criticality, permitted down-time, and the need to save data in order to effect a roll-back. The technology part stresses the impact of large scale integration (LSI) on the realization of logic and memory. Also considered was module interconnection possibilities so as to minimize fault propagation

Design-for-delay-testability techniques for high-speed digital circuits

The importance of delay faults is enhanced by the ever increasing clock rates and decreasing geometry sizes of nowadays' circuits. This thesis focuses on the development of Design-for-Delay-Testability (DfDT) techniques for high-speed circuits and embedded cores. The rising costs of IC testing and in particular the costs of Automatic Test Equipment are major concerns for the semiconductor industry. To reverse the trend of rising testing costs, DfDT is\ud getting more and more important

Measurements, Models, Systems and Design

531 s.

High voltage DC switchgear development for multi-kW space power system: Aerospace technology development of three types of solid state power controllers for 200-1100VDC with current ratings of 25, 50, and 80 amperes with one type utilizing an electromechanical device

Three types of solid state power controllers (SSPC's) for high voltage, high power DC system applications were developed. The first type utilizes a SCR power switch. The second type employes an electromechanical power switch element with solid state commutation. The third type utilizes a transistor power switch. Significant accomplishments include high operating efficiencies, fault clearing, high/low temperature performance and vacuum operation

Testability and redundancy techniques for improved yield and reliability of CMOS VLSI circuits

The research presented in this thesis is concerned with the design of fault-tolerant integrated circuits as a contribution to the design of fault-tolerant systems. The economical manufacture of very large area ICs will necessitate the incorporation of fault-tolerance features which are routinely employed in current high density dynamic random access memories. Furthermore, the growing use of ICs in safety-critical applications and/or hostile environments in addition to the prospect of single-chip systems will mandate the use of fault-tolerance for improved reliability. A fault-tolerant IC must be able to detect and correct all possible faults that may affect its operation. The ability of a chip to detect its own faults is not only necessary for fault-tolerance, but it is also regarded as the ultimate solution to the problem of testing. Off-line periodic testing is selected for this research because it achieves better coverage of physical faults and it requires less extra hardware than on-line error detection techniques. Tests for CMOS stuck-open faults are shown to detect all other faults. Simple test sequence generation procedures for the detection of all faults are derived. The test sequences generated by these procedures produce a trivial output, thereby, greatly simplifying the task of test response analysis. A further advantage of the proposed test generation procedures is that they do not require the enumeration of faults. The implementation of built-in self-test is considered and it is shown that the hardware overhead is comparable to that associated with pseudo-random and pseudo-exhaustive techniques while achieving a much higher fault coverage through-the use of the proposed test generation procedures. The consideration of the problem of testing the test circuitry led to the conclusion that complete test coverage may be achieved if separate chips cooperate in testing each other's untested parts. An alternative approach towards complete test coverage would be to design the test circuitry so that it is as distributed as possible and so that it is tested as it performs its function. Fault correction relies on the provision of spare units and a means of reconfiguring the circuit so that the faulty units are discarded. This raises the question of what is the optimum size of a unit? A mathematical model, linking yield and reliability is therefore developed to answer such a question and also to study the effects of such parameters as the amount of redundancy, the size of the additional circuitry required for testing and reconfiguration, and the effect of periodic testing on reliability. The stringent requirement on the size of the reconfiguration logic is illustrated by the application of the model to a typical example. Another important result concerns the effect of periodic testing on reliability. It is shown that periodic off-line testing can achieve approximately the same level of reliability as on-line testing, even when the time between tests is many hundreds of hours

Cost-Effective Model Predictive Control Techniques for Modular Multilevel Converters

In this thesis, model predictive control (MPC) techniques are investigated with their applications to modular multilevel converters (MMCs). Since normally a large number of submodule (SM) capacitor voltages and gate signals need to be handled in an MMC, the MPC schemes studied in this thesis are employed for determining only the voltage levels of converter arms, while gate signals are subsequently generated by the conventional sorting method. Emphasis is given to inner-loop current control in terms of phase current and circulating current, aiming at performance enhancement and computation reduction. A variable rounding level control (VRLC) approach is developed in this thesis, which is based on a modification of the conventional nearest level control (NLC) scheme: instead of the conventional nearest integer function, a proper rounding function is selected for each arm of the MMC employing the MPC method. As a result, the simplicity of the NLC is maintained while the current regulating ability is improved. The VRLC technique can also be generalized from an MPC perspective. Different current controllers can be considered to generate the arm voltage references as input of the VRLC block, thus refining the control sets of the MPC. Based on the decoupled current models, the accumulated effect of SM capacitor voltage ripples is investigated, revealing that the VRLC strategy may not achieve a proper performance if the accumulated ripple is nontrivial compared to the voltage per level. Two indexes are also proposed for quantifying the current controllability of the VRLC. Benefiting from this analysis, A SM-grouping solution is put forward to apply such MPC techniques to an MMC with a large number of SMs, leading to an equivalent operation of an MMC with much reduced number of SMs, which significantly increases the current regulating capability with reduced complexity. As an example, the SM-grouping VRLC proposal is analyzed and its system design principles are described. This thesis also develops another MPC technique which directly optimizes the cost function using quadratic programming technique. Both a rigorous and a simplified procedure are provided to solve the optimization problem. Compared with the conventional finite control set (FCS)-MPC method which evaluates all voltage level combinations, the proposed scheme presents apparent advantage in terms of calculation cost while achieving similar performance