1 research outputs found
Programmable Switch as a Parallel Computing Device
Modern switches have packet processing capacity of up to multi-tera bits per
second, and they are also becoming more and more programmable. We seek to
understand whether the programmability can translate packet processing capacity
to computational power for parallel computing applications. In this paper, we
first develop a simple mathematical model to understand the costs and overheads
of data plane computation. Then we validate the the performance benefits of
offloading computation to network. Using experiments on real data center
network, we finnd that offloading computation to the data plane results in up
to 20x speed-up for a simple Map-Reduce application. Motivated by this, we
propose a parallel programming framework, p4mr, to help users efficiently
program multiple switches. We successfully build and test a prototype of p4mr
on a simulated testbed