메모리 인터페이스를 위한 4 레벨 펄스 진폭 변조 쿼터 레이트 수신기 설계

학위논문(박사) -- 서울대학교대학원 : 공과대학 전기·정보공학부, 2022. 8. 김수환.본 연구에서는 메모리 인터페이스를 위한 4 레벨 펄스 진폭 변조 (PAM-4) 수신기와 직교 클록을 생성하는 직교 신호 보정기를 제안된다. 데이터 센터에서 증가하는 IP 트래픽은 고속 및 저전력 메모리 인터페이스에 대한 수요를 증가시켜왔다. 이러한 요구를 만족시키기 위해 클럭 및 나이퀴스트 주파수를 높이지 않고도 데이터 전송률을 높일 수 있는 PAM-4 신호가 주목을 받고 있다. PAM-4 신호는 제로 비 복귀 신호 (NRZ) 보다 3배 낮은 수직 마진을 가지며, 이는 결정 피드백 이퀄라이저 내 슬라이스의 클럭-큐 딜레이를 증가시키며, 이로 인해 PAM-4 결정 피드백 이퀄라이저의 성능을 제한하는 요인이다. 본 연구에서는 인버터 기반의 합산기를 이용, 선택적으로 신호를 증폭시키는 결정 피드백 이퀄라이저를 사용함으로써 슬라이서의 전력 소모를 증가시키지 않으면서 슬라이서의 클럭-큐 딜레이를 줄일 수 있다. 또한, 적응형 지연 이득 컨트롤러를 포함하는 직교 신호 보정기는 높은 정확도와 빠른 스큐 보정으로 쿼드러처 클럭 간의 스큐를 교정할 수 있다. 선택적 눈 증폭 결정 피드백 이퀄라이저와 적응형 지연 이득 컨트롤러를 포함하는 직교 신호 보정기의 성능을 검증하기 위해 프로토타입 칩을 제작하였다. 제작된 칩은 65 nm CMOS 공정으로 제작되었다. 프로토타입 칩은 24 Gb/s/pin 에서 10-12 의 비트 에러율을 100 mUI 의 신호 너비로 달성하였다. 프로토타입 칩 내 PAM-4 수신기는 0.73 pJ/b 의 에너지 효율을 갖는다. 또한 적응형 지연 이득 컨트롤러를 포함하는 직교 신호 보정기는 3 GHz 쿼드러처 클럭 간 최대 21.2 ps 의 스큐를 0.8 ps 까지 줄일 수 있으며, 이 때 76.9 ns 의 교정 시간을 갖는다. 제안하는 직교 신호 보정기는 3 GHz 에서 2.15 mW/GHz 의 전력 효율을 갖는다.A four-level pulse amplitude modulation (PAM-4) receiver, and a quadrature signal corrector (QSC) that generates quadrature clocks for memory interfaces is presented. Increasing IP traffic in data centers has increased the demand for high-speed and low-power memory interfaces. To satisfy this demand, PAM-4 signaling, which can increase data-rate without increasing clock and Nyquist frequency, is received considerable attention. PAM- signaling has vertical which three times lower than non-return-to-zero (NRZ) signaling, which makes the clock-to-Q delay of the slicer in the decision feedback equalizer (DFE) increases. This makes the DFE difficult to satisfy the timing constraint. In this paper, by using a DFE with inverter-based summers, the clock-to-Q delay of the slicer can be reduced without increasing the power consumption of the slicers. Also, the QSC using an adaptive delay gain controller can correct the skew between the quadrature clock with low skew and short correction time. The prototype receiver including the DFE with the inverter-based summer and the QSC using the adaptive delay gain controller was fabricated in 65 nm CMOS process. The prototype chip can achieve a bit error rate (BER) of 10-12 at 24 Gb/s/pin, and at this time, an eye width of 100 mUI is secured. The efficiency of the receiver is 0.73 pJ/b. In addition, the QSC cna reduce the maximum 21.2 ps of skew between 3 GHz quadrature clocks to 0.8 ps and has a correction time of 76.9 ns. The efficiency of the QSC is 2.15 mW/GHz.ABSTRACT 1 CONTENTS 3 LIST OF FIGURES 5 LIST OF TABLE 9 CHAPTER 1 1 INTRODUCTION 1 1.1 MOTIVATION 1 1.2 PAM-4 SIGNALING 7 1.2.1 DESIGN CONSIDERATIONS ON PAM-4 RECEIVER 10 1.2.2 PRIOR WORKS 14 1.3 QUARTER-RATE ARCHITECTURE 18 1.3.1 DESIGN CONSIDERATION ON QUARTER-RATE ARCHITECTURE 20 1.3.2 PRIOR WORKS 25 1.4 SUMMARY 28 1.5 THESIS ORGANIZATION 30 CHAPTER 2 31 CONCEPTS OF DFE WITH INVERTER-BASED SUMMER 31 2.1 CONCEPTUAL ARCHITECTURE OF DFE WITH INVERTER-BASED SUMMER 32 2.2 DESIGN CONSIDERATION OF INVERTER-BASED SUMMER 37 CHAPTER 3 41 CONCEPTS OF QUADRATURE SIGNAL CORRECTOR USING ADAPTIVE DELAY GAIN CONTROLLER 41 3.1 OPERATION OF PROPOSED QUADRATURE SIGNAL CORRECTOR 42 3.2 LOOP FILTER INCLUDING ADAPTIVE DELAY GAIN CONTROLLER 45 CHAPTER 4 48 ARCHITECTURE AND IMPLEMENTATION 48 4.1 OVERALL ARCHITECTURE 49 4.2 ANALOG FRONT END 52 4.3 DECISION FEEDBACK EQUALIZER WITH INVERTER-BASED SUMMER 54 4.4 CLOCK PATH 62 4.5 QUADRATURE SIGNAL CORRECTOR WITH ADAPTIVE DELAY GAIN CONTROLLER 63 CHAPTER 5 70 EXPERIMENTAL RESULTS 70 5.1 EXPERIMENTAL SETUP 70 5.2 EXPERIMENTAL RESULTS 74 5.2.1 MEASUREMENT RESULTS OF PAM-4 RECEIVER WITH DECISION FEEDBACK EQUALIZER USING INVERTER-BASED SUMMER 74 5.2.2 MEASUREMENT RESULTS OF QUADRATURE SIGNAL CORRECTOR USING ADAPTIVE DELAY GAIN CONTROLLER 77 CHAPTER 6 83 CONCLUSION 83 BIBLIOGRAPHY 86박

데이터 전송로 확장성과 루프 선형성을 향상시킨 다중채널 수신기들에 관한 연구

학위논문 (박사)-- 서울대학교 대학원 : 전기·컴퓨터공학부, 2013. 2. 정덕균.Two types of serial data communication receivers that adopt a multichannel architecture for a high aggregate I/O bandwidth are presented. Two techniques for collaboration and sharing among channels are proposed to enhance the loop-linearity and channel-expandability of multichannel receivers, respectively. The first proposed receiver employs a collaborative timing scheme recovery which relies on the sharing of all outputs of phase detectors (PDs) among channels to extract common information about the timing and multilevel signaling architecture of PAM-4. The shared timing information is processed by a common global loop filter and is used to update the phase of the voltage-controlled oscillator with better rejection of per-channel noise. In addition to collaborative timing recovery, a simple linearization technique for binary PDs is proposed. The technique realizes a high-rate oversampling PD while the hardware cost is equivalent to that of a conventional 2x-oversampling clock and data recovery. The first receiver exploiting the collaborative timing recovery architecture is designed using 45-nm CMOS technology. A single data lane occupies a 0.195-mm2 area and consumes a relatively low 17.9 mW at 6 Gb/s at 1.0V. Therefore, the power efficiency is 2.98 mW/Gb/s. The simulated jitter is about 0.034 UI RMS given an input jitter value of 0.03 UI RMS, while the relatively constant loop bandwidth with the PD linearization technique is about 7.3-MHz regardless of the data-stream noise. Unlike the first receiver, the second proposed multichannel receiver was designed to reduce the hardware complexity of each lane. The receiver employs shared calibration logic among channels and yet achieves superior channel expandability with slim data lanes. A shared global calibration control, which is used in a forwarded clock receiver based on a multiphase delay-locked loop, accomplishes skew calibration, equalizer adaptation, and the phase lock of all channels during a calibration period, resulting in reduced hardware overhead and less area required by each data lane. The second forwarded clock receiver is designed in 90-nm CMOS technology. It achieves error-free eye openings of more than 0.5 UI across 9− 28 inch Nelco 4000-6 microstrips at 4− 7 Gb/s and more than 0.42 UI at data rates of up to 9 Gb/s. The data lane occupies only 0.152 mm2 and consumes 69.8 mW, while the rest of the receiver occupies 0.297 mm2 and consumes 56 mW at a data rate of 7 Gb/s and a supply voltage of 1.35 V.1. Introduction 1 1.1 Motivations 1.2 Thesis Organization 2. Previous Receivers for Serial-Data Communications 2.1 Classification of the Links 2.2 Clocking architecture of transceivers 2.3 Components of receiver 2.3.1 Channel loss 2.3.2 Equalizer 2.3.3 Clock and data recovery circuit 2.3.3.1. Basic architecture 2.3.3.2. Phase detector 2.3.3.2.1. Linear phase detector 2.3.3.2.2. Binary phase detector 2.3.3.3. Frequency detector 2.3.3.4. Charge pump 2.3.3.5. Voltage controlled oscillator and delay-line 2.3.4 Loop dynamics of PLL 2.3.5 Loop dynamics of DLL 3. The Proposed PLL-Based Receiver with Loop Linearization Technique 3.1 Introduction 3.2 Motivation 3.3 Overview of binary phase detection 3.4 The proposed BBPD linearization technique 3.4.1 Architecture of the proposed PLL-based receiver 3.4.2 Linearization technique of binary phase detection 3.4.3 Rotational pattern of sampling phase offset 3.5 PD gain analysis and optimization 3.6 Loop Dynamics of the 2nd-order CDR 3.7 Verification with the time-accurate behavioral simulation 3.8 Summary 4. The Proposed DLL-Based Receiver with Forwarded-Clock 4.1 Introduction 4.2 Motivation 4.3 Design consideration 4.4 Architecture of the proposed forwarded-clock receiver 4.5 Circuit description 4.5.1 Analog multi-phase DLL 4.5.2 Dual-input interpolating deley cells 4.5.3 Dedicated half-rate data samplers 4.5.4 Cherry-Hooper continuous-time linear equalizer 4.5.5 Equalizer adaptation and phase-lock scheme 4.6 Measurement results 5. Conclusion 6. BibliographyDocto

INJECTION-LOCKING TECHNIQUES FOR MULTI-CHANNEL ENERGY EFFICIENT TRANSMITTER

Ph.DDOCTOR OF PHILOSOPH

Design Techniques for Energy Efficient Multi-GB/S Serial I/O Transceivers

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Power-efficient wireline transceivers are highly demanded by many applications in high performance computation and communication systems. Apart from transferring a wide range of data rates to satisfy the interconnect bandwidth requirement, the transceivers have very tight power budget and are expected to be fully integrated. This thesis explores enabling techniques to implement such transceivers in both circuit and system levels. Specifically, three prototypes will be presented: (1) a 5Gb/s reference-less clock and data recovery circuit (CDR) using phase-rotating phase-locked loop (PRPLL) to conduct phase control so as to break several fundamental trade-offs in conventional receivers; (2) a 4-10.5Gb/s continuous-rate CDR with novel frequency acquisition scheme based on bang-bang phase detector (BBPD) and a ring oscillator-based fractional-N PLL as the low noise wide range DCO in the CDR loop; (3) a source-synchronous energy-proportional link with dynamic voltage and frequency scaling (DVFS) and rapid on/off (ROO) techniques to cut the link power wastage at system level. The receiver/transceiver architectures are highly digital and address the requirements of new receiver architecture development, wide operating range, and low power/area consumption while being fully integrated. Experimental results obtained from the prototypes attest the effectiveness of the proposed techniques

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Numerical Simulations

This book will interest researchers, scientists, engineers and graduate students in many disciplines, who make use of mathematical modeling and computer simulation. Although it represents only a small sample of the research activity on numerical simulations, the book will certainly serve as a valuable tool for researchers interested in getting involved in this multidisciplinary field. It will be useful to encourage further experimental and theoretical researches in the above mentioned areas of numerical simulation

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The electric vehicle and plug-in hybrid electric vehicle play a fundamental role in the forthcoming new paradigms of mobility and energy models. The electrification of the transport sector would lead to advantages in terms of energy efficiency and reduction of greenhouse gas emissions, but would also be a great opportunity for the introduction of renewable sources in the electricity sector. The chapters in this book show a diversity of current and new developments in the electrification of the transport sector seen from the electric vehicle point of view: first, the related technologies with design, control and supervision, second, the powertrain electric motor efficiency and reliability and, third, the deployment issues regarding renewable sources integration and charging facilities. This is precisely the purpose of this book, that is, to contribute to the literature about current research and development activities related to new trends in electric vehicle power trains.Peer ReviewedPostprint (author's final draft