Process Variation Aware Parallelization Strategies for MPSoCs

Scaling of microprocessors is aggravating the gap between design and manufacturing expectations. Such variations may lead to manufacturing of processors cores with frequencies lower or higher than their expected frequencies. In particular, with the rapid advent of Multiprocessor System on Chips (MPSoC), such manufacturing uncertainties may lead to significant variations in the operating frequencies of different processors cores on the same chip. In this work, we demonstrate that traditional load balanced parallelization schemes need to be revisited to account for such variations. Specifically, we show the need for tuning the degree of parallelization and non-uniform workload generation to achieve lower power consumption in the presence of process variations