Probabilistic Optimization for FPGA Board Level Routing Problems

Abstract—Field programmable gate arrays (FPGAs) are an enabling technology in circuit designs. We consider the board-level multi-terminal net assignment in the FPGA-based logic emulation. A novel probabilistic optimization method is devised for solving the net assignment problem. The approach incorporates randomized rounding, genetic algorithm, and solution-improvement strategies. Experimental results demonstrate promising performance. Index Terms—Board-level routing, Chernoff bound, field programmable gate array (FPGA), randomized rounding