Equivalence checking of retimed circuits

Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2005.This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.Includes bibliographical references (p. 25).This thesis addresses the problem of verifying the equivalence of two circuits, one or both of which have undergone register retiming as well as logic resynthesis. The aim of the thesis is to improve the ability of Formality, an equivalence checking tool written at Synopsys, to handle retimed circuits. At the beginning of this project Formality already had an implementation of peripheral retiming, an algorithm that can handle a large set of retimed circuits. In this thesis, I explain the performance, usability and special case coverage problems found in the original implementation. I review other retiming verification algorithms and conclude that none of them would perform satisfactorily in Formality. Finally, I explain the modifications made to peripheral retiming in order to solve some of the identified issues and propose partial solutions for the problems that have not been solved yet.by Karolína Netolická.M.Eng

Feed-Forward Propagation of Temporal and Rate Information between Cortical Populations during Coherent Activation in Engineered In Vitro Networks.

Transient propagation of information across neuronal assembles is thought to underlie many cognitive processes. However, the nature of the neural code that is embedded within these transmissions remains uncertain. Much of our understanding of how information is transmitted among these assemblies has been derived from computational models. While these models have been instrumental in understanding these processes they often make simplifying assumptions about the biophysical properties of neurons that may influence the nature and properties expressed. To address this issue we created an in vitro analog of a feed-forward network composed of two small populations (also referred to as assemblies or layers) of living dissociated rat cortical neurons. The populations were separated by, and communicated through, a microelectromechanical systems (MEMS) device containing a strip of microscale tunnels. Delayed culturing of one population in the first layer followed by the second a few days later induced the unidirectional growth of axons through the microtunnels resulting in a primarily feed-forward communication between these two small neural populations. In this study we systematically manipulated the number of tunnels that connected each layer and hence, the number of axons providing communication between those populations. We then assess the effect of reducing the number of tunnels has upon the properties of between-layer communication capacity and fidelity of neural transmission among spike trains transmitted across and within layers. We show evidence based on Victor-Purpura's and van Rossum's spike train similarity metrics supporting the presence of both rate and temporal information embedded within these transmissions whose fidelity increased during communication both between and within layers when the number of tunnels are increased. We also provide evidence reinforcing the role of synchronized activity upon transmission fidelity during the spontaneous synchronized network burst events that propagated between layers and highlight the potential applications of these MEMs devices as a tool for further investigation of structure and functional dynamics among neural populations

Heuristics Based Test Overhead Reduction Techniques in VLSI Circuits

The electronic industry has evolved at a mindboggling pace over the last five decades. Moore’s Law [1] has enabled the chip makers to push the limits of the physics to shrink the feature sizes on Silicon (Si) wafers over the years. A constant push for power-performance-area (PPA) optimization has driven the higher transistor density trends. The defect density in advanced process nodes has posed a challenge in achieving sustainable yield. Maintaining a low Defect-per-Million (DPM) target for a product to be viable with stringent Time-to-Market (TTM) has become one of the most important aspects of the chip manufacturing process. Design-for-Test (DFT) plays an instrumental role in enabling low DPM. DFT however impacts the PPA of a chip. This research describes an approach of minimizing the scan test overhead in a chip based on circuit topology heuristics. These heuristics are applied on a full-scan design to convert a subset of the scan flip-flops (SFF) into D flip-flops (DFF). The K Longest Path per Gate (KLPG) [2] automatic test pattern generation (ATPG) algorithm is used to generate tests for robust paths in the circuit. Observability driven multi cycle path generation [3][4] and test are used in this work to minimize coverage loss caused by the SFF conversion process. The presence of memory arrays in a design exacerbates the coverage loss due to the shadow cast by the array on its neighboring logic. A specialized behavioral modeling for the memory array is required to enable test coverage of the shadow logic. This work develops a memory model integrated into the ATPG engine for this purpose. Multiple clock domains pose challenges in the path generation process. The inter-domain clocking relationship and corresponding logic sensitization are modeled in our work to generate synchronous inter-domain paths over multiple clock cycles. Results are demonstrated on ISCAS89 and ITC99 benchmark circuits. Power saving benefit is quantified using an open-source standard-cell library

The pseudo-exhaustive test of sequential circuits

The concept of a pseudoexhaustive test for sequential circuits is introduced. Instead of test sets one applies pseudoexhaustive test sequences of a limited length, which provides well-known benefits as far as fault coverage, self-test capability, and simplicity of test generation are concerned. Some flip flops and latches are integrated into an incomplete scan path, such that each possible state of the circuit is reachable within a few steps. Some more flip flops and some new segmentation cells are added to the partial scan path in order to make a pseudoexhaustive test feasible. Algorithms for placing these devices automatically are presented. Also it is shown how to transform a pseudoexhaustive test set into a pseudoexhaustive test sequence of a similar size. The analyzed examples show that a conventional complete scan path without additional testability features requires more hardware overhead than the proposed test strategy, which retains all the known benefits of a pseudoexhaustive test

Doctor of Philosophy

dissertationIn Chapter 1, an introduction to basic principles or MRI is given, including the physical principles, basic pulse sequences, and basic hardware. Following the introduction, five different published and yet unpublished papers for improving the utility of MRI are shown. Chapter 2 discusses a small rodent imaging system that was developed for a clinical 3 T MRI scanner. The system integrated specialized radiofrequency (RF) coils with an insertable gradient, enabling 100 'm isotropic resolution imaging of the guinea pig cochlea in vivo, doubling the body gradient strength, slew rate, and contrast-to-noise ratio, and resulting in twice the signal-to-noise (SNR) when compared to the smallest conforming birdcage. Chapter 3 discusses a system using BOLD MRI to measure T2* and invasive fiberoptic probes to measure renal oxygenation (pO2). The significance of this experiment is that it demonstrated previously unknown physiological effects on pO2, such as breath-holds that had an immediate (<1 sec) pO2 decrease (~6 mmHg), and bladder pressure that had pO2 increases (~6 mmHg). Chapter 4 determined the correlation between indicators of renal health and renal fat content. The R2 correlation between renal fat content and eGFR, serum cystatin C, urine protein, and BMI was less than 0.03, with a sample size of ~100 subjects, suggesting that renal fat content will not be a useful indicator of renal health. Chapter 5 is a hardware and pulse sequence technique for acquiring multinuclear 1H and 23Na data within the same pulse sequence. Our system demonstrated a very simple, inexpensive solution to SMI and acquired both nuclei on two 23Na channels using external modifications, and is the first demonstration of radially acquired SMI. Chapter 6 discusses a composite sodium and proton breast array that demonstrated a 2-5x improvement in sodium SNR and similar proton SNR when compared to a large coil with a linear sodium and linear proton channel. This coil is unique in that sodium receive loops are typically built with at least twice the diameter so that they do not have similar SNR increases. The final chapter summarizes the previous chapters

An asynchronous instruction length decoder

Journal ArticleAbstract-This paper describes an investigation of potential advantages and pitfalls of applying an asynchronous design methodology to an advanced microprocessor architecture. A prototype complex instruction set length decoding and steering unit was implemented using self-timed circuits. [The Revolving Asynchronous Pentium® Processor Instruction Decoder (RAPPID) design implemented the complete Pentium II® 32-bit MMX instruction set.] The prototype chip was fabricated on a 0.25-CMOS process and tested successfully. Results show significant advantages-in particular, performance of 2.5-4.5 instructions per nanosecond-with manageable risks using this design technology. The prototype achieves three times the throughput and half the latency, dissipating only half the power and requiring about the same area as the fastest commercial 400-MHz clocked circuit fabricated on the same process

The pseudoexhaustive test of sequential circuits

The concept of a pseudoexhaustive test for sequential circuits is introduced in a way similar to that which is used for combinational networks. Using partial scan all cycles in the data flow of a sequential circuit are removed, such that a compact combinational model can be constructed. Pseudoexhaustive test sequences for the original circuit are constructed from a pseudoexhaustive test set for this model. To make this concept feasible for arbitrary circuits a technique for circuit segmentation is presented which provides special segmentation cells as well as the corresponding algorithms for the automatic placement of the cells. Example circuits show that the test strategy requires less additional silicon area than a complete scan path. Thus the advantages of a partial scan path are combined with the well-known benefits of a pseudoexhaustive test, such as high fault coverage and simplified test generation

論理シミュレーションとハードウェア記述言語に関する研究

京都大学0048新制・論文博士工学博士乙第7496号論工博第2471号新制||工||842(附属図書館)UT51-91-E273(主査)教授 矢島 脩三, 教授 津田 孝夫, 教授 田丸 啓吉学位規則第5条第2項該当Kyoto UniversityDFA

An asynchronous instruction length decoder

Journal ArticleThis paper describes an investigation of potential advantages and pitfalls of applying an asynchronous design methodology to an advanced microprocessor architecture. A prototype complex instruction set length decoding and steering unit was implemented using self-timed circuits. [The Revolving Asynchronous Pentium® Processor Instruction Decoder (RAPPID) design implemented the complete Pentium II® 32-bit MMX instruction set.] The prototype chip was fabricated on a 0.25-CMOS process and tested successfully. Results show significant advantages-in particular, performance of 2.5-4.5 instructions per nanosecond-with manageable risks using this design technology. The prototype achieves three times the throughput and half the latency, dissipating only half the power and requiring about the same area as the fastest commercial 400-MHz clocked circuit fabricated on the same process