Estimating data-dependent jitter of a general LTI system from step response

We present a method for estimating data dependent jitter (DDJ) introduced by a general LTI system, based on the system's step response. A perturbation technique is used to generalize the analytical expression for DDJ. Different scales of DDJ are defined that characterize the probability distribution of jitter. In particular, we identify a dominant prior bit that signifies the well-known distribution of DDJ, the two impulse functions. We also highlight that system bandwidth is not a complete measure for predicting DDJ. We verify our generalized analytical expression of DDJ experimentally and show that estimation errors are less than 7.5%

A 10Gb/s data-dependent jitter equalizer

An equalization circuit is presented that reduces data-dependent jitter by aligning data transition deviations. This paper presents an analytic solution to data-dependent jitter and demonstrates its impact on the phase noise of the recovered clock. A data-dependent jitter equalizer is presented that compensates for impairment of the channel and lowers the phase noise of the recovered clock. The circuit is implemented in a SiGe BiCMOS process and operates at 10 Gb/s. It suppresses phase noise resulting from data-dependent jitter by 10 dB

Analysis and equalization of data-dependent jitter

Data-dependent jitter limits the bit-error rate (BER) performance of broadband communication systems and aggravates synchronization in phase- and delay-locked loops used for data recovery. A method for calculating the data-dependent jitter in broadband systems from the pulse response is discussed. The impact of jitter on conventional clock and data recovery circuits is studied in the time and frequency domain. The deterministic nature of data-dependent jitter suggests equalization techniques suitable for high-speed circuits. Two equalizer circuit implementations are presented. The first is a SiGe clock and data recovery circuit modified to incorporate a deterministic jitter equalizer. This circuit demonstrates the reduction of jitter in the recovered clock. The second circuit is a MOS implementation of a jitter equalizer with independent control of the rising and falling edge timing. This equalizer demonstrates improvement of the timing margins that achieve 10/sup -12/ BER from 30 to 52 ps at 10 Gb/s

Phase and amplitude pre-emphasis techniques for low-power serial links

A novel approach to equalization of high-speed serial links combines both amplitude pre-emphasis to correct for intersymbol interference and phase pre-emphasis to compensate for deterministic jitter, in particular, data-dependent jitter. Phase pre-emphasis augments the performance of low power transmitters in bandwidth-limited channels. The transmitter circuit is implemented in a 90-nm bulk CMOS process and reduces power consumption by pushing CMOS static logic to the output stage, a 4:1 output multiplexer. The received signal jitter over a cable is reduced from 16.15 ps to 10.29 ps with only phase pre-emphasis at the transmitter. The jitter is reduced by 3.6 ps over an FR-4 backplane interconnect. A transmitter without phase pre-emphasis consumes 18 mW of power at 6Gb/s and 600mVpp output swing, a power budget of 3mW/Gb/s, while a transmitter with phase pre-emphasis consumes 24mW, a budget of 4 mW/Gb/s

Instantaneous Clockless Data Recovery and Demultiplexing

An alternative architecture for instantaneous data recovery for burst-mode communication is introduced. The architecture can perform 1:n demultiplexing without additional clock recovery phase-locked loop or sampling blocks. A finite-state machine (FSM) is formed with combinational logic and analog LC transmission line delay cells in a feedback loop. The FSM responds to input data transitions instantaneously and sets the outputs. The system reduces unit interval jitter by a factor of n. The new architecture is demonstrated via a SiGe 1:2 clockless demultiplexer circuit that operates at 7.5 Gb/s

Effect of Jitter on the Settling Time of Mesochronous Clock Retiming Circuits

It is well known that timing jitter can degrade the bit error rate (BER) of receivers that recover the clock from input data. However, timing jitter can also result in an indefinite increase in the settling time of clock recovery circuits, particularly in low swing mesochronous systems. Mesochronous clock retiming circuits are required in repeaterless low swing on-chip interconnects. We first discuss how timing jitter can result in a large increase in the settling time of the clock recovery circuit. Next, the circuit is modelled as a Markov chain with absorbing states. The mean time to absorption of the Markov chain, which represents the mean settling time of the circuit, is determined. The model is validated through behavioural simulations of the circuit, the results of which match well with the model predictions. We consider circuits with (i) data dependent jitter, (ii) random jitter, and (iii) combination of both of them. We show that a mismatch between the strengths of up and down corrections of the retiming can reduce the settling time. In particular, a 10% mismatch can reduce the mean settling time by up to 40%. We leverage this fact toward improving the settling time performance, and propose useful techniques based on biased training sequences and mismatched charge pumps. We also present a coarse+fine clock retiming circuit, which can operate in coarse first mode, to reduce the settling time substantially. These fast settling retiming circuits are verified with circuit simulations.Comment: 23 pages, 40 figure