Product assurance technology for custom LSI/VLSI electronics

The technology for obtaining custom integrated circuits from CMOS-bulk silicon foundries using a universal set of layout rules is presented. The technical efforts were guided by the requirement to develop a 3 micron CMOS test chip for the Combined Release and Radiation Effects Satellite (CRRES). This chip contains both analog and digital circuits. The development employed all the elements required to obtain custom circuits from silicon foundries, including circuit design, foundry interfacing, circuit test, and circuit qualification

Product assurance technology for procuring reliable, radiation-hard, custom LSI/VLSI electronics

Advanced measurement methods using microelectronic test chips are described. These chips are intended to be used in acquiring the data needed to qualify Application Specific Integrated Circuits (ASIC's) for space use. Efforts were focused on developing the technology for obtaining custom IC's from CMOS/bulk silicon foundries. A series of test chips were developed: a parametric test strip, a fault chip, a set of reliability chips, and the CRRES (Combined Release and Radiation Effects Satellite) chip, a test circuit for monitoring space radiation effects. The technical accomplishments of the effort include: (1) development of a fault chip that contains a set of test structures used to evaluate the density of various process-induced defects; (2) development of new test structures and testing techniques for measuring gate-oxide capacitance, gate-overlap capacitance, and propagation delay; (3) development of a set of reliability chips that are used to evaluate failure mechanisms in CMOS/bulk: interconnect and contact electromigration and time-dependent dielectric breakdown; (4) development of MOSFET parameter extraction procedures for evaluating subthreshold characteristics; (5) evaluation of test chips and test strips on the second CRRES wafer run; (6) two dedicated fabrication runs for the CRRES chip flight parts; and (7) publication of two papers: one on the split-cross bridge resistor and another on asymmetrical SRAM (static random access memory) cells for single-event upset analysis

Design and Analysis of a Wide Loop-Bandwidth RF Synthesizer Using Ring oscillator For DECT Receiver

Wireless communication devices including cordless phones and modern digital cellular systems (DCSs) use portable transceiver systems. The frequency synthesis of this type of transceiver system is done using a phase-locked loop oscillator. Traditional on-chip implementation of a complete phase-locked loop using a ring type voltage controlled oscillator contributes higher noise at the output. An alternative architecture, phase-locked loop (PLL) with wide loop-bandwidth, is proposed in this research to suppress the noise from the traditional ring oscillator. The proposed PLL is amendable to on-chip integration as well as commercially suitable for a Digital Enhancement Cordless Telephone (DECT) system which needs flexible noise margin. In this research, a 1.5552 GHz PLL-based frequency synthesizer is designed with a noisy ring oscillator. The wide loop-bandwidth approach is applied in designing the PLL to suppress the VCO noise. In this type of frequency synthesizer, the frequency divider is operated at higher frequencies with less noise and care is taken to design the delay flip-flops and logic gates that can be operated at higher frequencies. Current-mode control can be employed in designing the logic gates and the delay flip-flop to enhance the speed performance of the divider. An alternate approach in designing a high-speed divider using a current-mode control approach is also presented

Combined C-V/I-V and RTN CMOS Variability Characterization Using An On-Chip Measurement System

With the number of transistors integrated into a single integrated circuit (IC) crossing the one-billion mark and complementary metal-oxide-semiconductor (CMOS) technology scaling pushing device dimensions ever-so-close to atomic scales, variability in transistor performance is becoming the dominant constraint in modern-day CMOS IC design. Developing novel approaches for device characterization, which allow a detailed study of electrical transistor characteristics across large statistical sample sets, is crucial for the proper identification, characterization, and modeling of different physical sources of device variability. On-chip characterization methodologies have the potential to address all of these issues by enabling the characterization of large statistical device sample sets, while also allowing for high measurement quality and throughput. In this work, a fully-integrated system for on-chip combined capacitance-voltage (C-V) and current-voltage (I-V) characterization of a large integrated test transistor array implemented in a 45-nm bulk CMOS process is presented. On-chip I-V characterization is implemented using a four-point Kelvin measurement technique with 12-bit sub-10 nA current measurement resolution, 10-bit sub-1 mV voltage measurement resolution, and sampling speeds on the order of 100 kHz. C-V characterization is performed using a novel leakage- and parasitics-insensitive charge-based capacitance measurement (CBCM) technique with atto-Farad resolution. The on-chip system is employed in developing a comprehensive CMOS transistor variability characterization methodology, studying both random and systematic sources of quasi-static device variability. For the first time, combined C-V/I-V characterization of circuit-representative devices is demonstrated and used to extract variations in the under- lying physical parameters of the device. Additionally, the fast current sampling capabilities of the system are used for the characterization of random telegraph noise (RTN) in small area devices. An automated methodology for the extraction of RTN parameters is developed, and the statistics of RTN are studied across device type, bias, and geometry

On-chip NBTI and Gate-Oxide-Degradation Sensing and Dynamic Management in VLSI Circuits.

The VLSI industry has achieved advancement in technology by continuous process scaling which has resulted in large scale integration. However, scaling also poses new reliability challenges. Currently the industry ensures the reliability of chips by limiting the supply voltage and temperature, but these constraints limit the benefits that are obtained from new process nodes. This method of managing reliability during design time is called Static Reliability Management (SRM). While SRM ensures that all the chips meet the reliability specifications, it introduces extreme pessimism in the chips as it margins for worst process, voltage, temperature and circuit state (PVTS), which will not be required for the majority of chips. To reduce the pessimism of SRM, the system needs to be made aware of its reliability by employing degradation sensors or degradation detection techniques. Using the degradation measurements, the system can estimate its lifetime and can adjust its operating points (supply voltage and temperature limits) dynamically and trade excess reliability slack with performance. This method of reliability management is called Dynamic Reliability Management (DRM). In this work we investigate different methods of DRM. We focus on two critical degradation mechanisms: Negative Bias Temperature Instability (NBTI) and Gate-oxide degradation. We propose NBTI and Gate-oxide degradation sensors with low area and power overhead, which allows them to be deployed in large numbers on the chip enabling collection of degradation statistics. The sensors were designed in 130nm and 45nm process nodes and tested on two test-chips. We then used the sensors to perform DRM in a silicon test for the first time. We demonstrate that DRM eliminates excess reliability slack which allows for a boost in supply voltage and performance. We then propose in situ Bias Temperature Instability (BTI) and Gate-oxide wear-out detection techniques. The in situ technique measures the degradation in the actual devices in the core and removes all the layers of uncertainty which arise because of the statistical nature of degradation and its dependence on PVTS. We implemented and tested these techniques on two test chips in a 65nm process node. We then use the BTI sensing technique to perform DRM.Ph.D.Electrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/86281/1/prsingh_1.pd

Conceptual design and analysis of a large antenna utilizing electrostatic membrane management

Conceptual designs and associated technologies for deployment 100 m class radiometer antennas were developed. An electrostatically suspended and controlled membrane mirror and the supporting structure are discussed. The integrated spacecraft including STS cargo bay stowage and development were analyzed. An antenna performance evaluation was performed as a measure of the quality of the membrane/spacecraft when used as a radiometer in the 1 GHz to 5 GHz region. Several related LSS structural dynamic models differing by their stiffness property (and therefore, lowest modal frequencies) are reported. Control system whose complexity varies inversely with increasing modal frequency regimes are also reported. Interactive computer-aided-design software is discussed

Numerical simulation of sub-100 nm strained Si/SiGe MOSFETs for RF and CMOS applications

Drift-Diffusion, Hydrodynamic and Monte Carlo simulations have been used in this work to simulate strained Si/SiGe devices for RF and CMOS applications. For numerical simulations of Si/SiGe devices, strain effects on the band structure of Si have been analyzed and analytical expressions are presented for parameters related to the bandgap and band alignment of Si/SiGe heterostructure. Optimization of n-type buried strained Si channel Si/SiGe MODFETs has been carried out in order to achieve high RF performance and high linearity. The impact of both lateral and vertical device geometries and different doping strategies has been investigated. The impact of the Ge content of the SiGe buffer on the performance of p-type surface channel strained Si/SiGe MOSFETs has been studied. Hydrodynamic device simulations have been used to assess the device performance of p-type strained Si/SiGe MOSFETs down to 35 nm gate lengths. Well-tempered strained Si MOSFETs with halo implants around the source/drain regions have been simulated and compared with those devices possessing only a single retrograde channel doping. The calibrations in respect of sub-100 nm Si and strained Si MOSFETs fabricated by IBM lead to a scaling study of those devices at 65 nm, 45 nm and 35 nm gate lengths. Using Drift-Diffusion simulations, ring oscillator circuit behaviour has been evaluated. Strained Si on insulator (SSOI) circuits have also been simulated and compared with strained Si circuits, Si circuits employing conventional surface channel MOSFETs along with SOI devices. Ensemble Monte Carlo simulations have been used to evaluate the device performance of n-type strained Si MOSFETs. A non-perturbative interface roughness scattering model has been used and validated by calibrating with respect to experimental mobility behaviour and device characteristics. The impact of interface roughness on the performance enhancement of strained Si MOSFETs has been investigated and evidence for reduced interface roughness scattering is presented, i.e., a smoother interface is suggested in strained Si MOSFETs. A 35 nm gate length Toshiba Si MOSFET has been simulated and the performance enhancement of 35 nm strained Si MOSFETs over the Toshiba Si device is predicted. Monte Carlo simulations are also employed to investigate the performance degradation due to soft-optical phonon scattering, which arises with the introduction of high-K gate dielectrics. Based on the device structures of the calibrated sub-100 nm n-type conventional and strained Si IBM MOSFETs, significant current degradation has been observed in devices with high-K gate dielectrics, HfO2 and Al2O3

Physically-Adaptive Computing via Introspection and Self-Optimization in Reconfigurable Systems.

Digital electronic systems typically must compute precise and deterministic results, but in principle have flexibility in how they compute. Despite the potential flexibility, the overriding paradigm for more than 50 years has been based on fixed, non-adaptive inte-grated circuits. This one-size-fits-all approach is rapidly losing effectiveness now that technology is advancing into the nanoscale. Physical variation and uncertainty in com-ponent behavior are emerging as fundamental constraints and leading to increasingly sub-optimal fault rates, power consumption, chip costs, and lifetimes. This dissertation pro-poses methods of physically-adaptive computing (PAC), in which reconfigurable elec-tronic systems sense and learn their own physical parameters and adapt with fine granu-larity in the field, leading to higher reliability and efficiency. We formulate the PAC problem and provide a conceptual framework built around two major themes: introspection and self-optimization. We investigate how systems can efficiently acquire useful information about their physical state and related parameters, and how systems can feasibly re-implement their designs on-the-fly using the information learned. We study the role not only of self-adaptation—where the above two tasks are performed by an adaptive system itself—but also of assisted adaptation using a remote server or peer. We introduce low-cost methods for sensing regional variations in a system, including a flexible, ultra-compact sensor that can be embedded in an application and implemented on field-programmable gate arrays (FPGAs). An array of such sensors, with only 1% to-tal overhead, can be employed to gain useful information about circuit delays, voltage noise, and even leakage variations. We present complementary methods of regional self-optimization, such as finding a design alternative that best fits a given system region. We propose a novel approach to characterizing local, uncorrelated variations. Through in-system emulation of noise, previously hidden variations in transient fault sus-ceptibility are uncovered. Correspondingly, we demonstrate practical methods of self-optimization, such as local re-placement, informed by the introspection data. Forms of physically-adaptive computing are strongly needed in areas such as com-munications infrastructure, data centers, and space systems. This dissertation contributes practical methods for improving PAC costs and benefits, and promotes a vision of re-sourceful, dependable digital systems at unimaginably-fine physical scales.Ph.D.Computer Science & EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/78922/1/kzick_1.pd