1 research outputs found
Recommended from our members
Transactions in Relaxed Memory Architectures
The integration of transactions into hardware relaxed memory architectures is a topic of current research both
in industry and academia. In this paper, we provide a general architectural framework for the introduction of
transactions into models of relaxed memory in hardware, including the sc, tso, armv8 and ppc models. Our
framework incorporates flexible and expressive forms of transaction aborts and execution that have hitherto
been in the realm of software transactional memory. In contrast to software transactional memory, we account
for the characteristics of relaxed memory as a restricted form of distributed system, without a notion of global
time. We prove abstraction theorems to demonstrate that the programmer API matches the intuitions and
expectations about transactions