Probabilistic Graphical Models on Multi-Core CPUs using Java 8

In this paper, we discuss software design issues related to the development of parallel computational intelligence algorithms on multi-core CPUs, using the new Java 8 functional programming features. In particular, we focus on probabilistic graphical models (PGMs) and present the parallelisation of a collection of algorithms that deal with inference and learning of PGMs from data. Namely, maximum likelihood estimation, importance sampling, and greedy search for solving combinatorial optimisation problems. Through these concrete examples, we tackle the problem of defining efficient data structures for PGMs and parallel processing of same-size batches of data sets using Java 8 features. We also provide straightforward techniques to code parallel algorithms that seamlessly exploit multi-core processors. The experimental analysis, carried out using our open source AMIDST (Analysis of MassIve Data STreams) Java toolbox, shows the merits of the proposed solutions.Comment: Pre-print version of the paper presented in the special issue on Computational Intelligence Software at IEEE Computational Intelligence Magazine journa

Thickness Effect on the Solid-State Reaction of a Ni/GaAs System

Ni thin films with different thicknesses were grown on a GaAs substrate using the magnetron sputtering technique followed by in situ X-ray diffraction (XRD) annealing in order to study the solid-state reaction between Ni and GaAs substrate. The thickness dependence on the formation of the intermetallic phases was investigated using in situ and ex situ XRD, pole figures, and atom probe tomography (APT). The results indicate that the 20 nm-thick Ni film exhibits an epitaxial relation with the GaAs substrate, which is (001) Ni//(001) GaAs and [111] Ni//[110] GaAs after deposition. Increasing the film’s thickness results in a change of the Ni film’s texture. This difference has an impact on the formation temperature of Ni3GaAs. This temperature decreases simultaneously with the thickness increase. This is due to the coherent/incoherent nature of the initial Ni/GaAs interface. The Ni3GaAs phase decomposes into the binary and ternary compounds xNiAs and Ni3−xGaAs1−x at about 400 °C. Similarly to Ni3GaAs, the decomposition temperature of the second phase also depends on the initial thickness of the Ni layer

Spatial control of electron & hole states in InAs/GaSb heterostructures

Single nanowire transistors employing three separately controlled electrostatic gates were fabricated to investigate band gap modulation in InAs-GaSb heterostructures. The aim is to show hybridization between electron and hole states over the heterojunction. Electric and thermoelectric characterization at low temperatures suggests that transport can be tuned from electrons in InAs to holes GaSb and that the relative band alignment can be altered from an inverted to a small effective gap. The band gap modulation is speculated to be caused by quantum confinement induced by the gates

Hall Measurement on Regrown Nanowires

Ternary semiconductor alloys like $In_xGa_{1-x}As$ have lured competing attention in connection to sub-50 nm high performance, low power, planar Complementary Metal Oxide Semiconductor technology. This compound semiconductor owes its popularity to excellent bulk carrier mobility, minority carrier diffusion constant, small bandgap, high electron injection velocity and its capability to take Moore's law beyond silicon platform. Though they exhibit exceptional properties in their bulk, their properties in confined architectures like a nanowire (NW) still remains relatively less explored. In this work, the transport properties of $In_xGa_{1-x}As$ is explored in a planar confined device architecture, by performing \textbf{Hall Measurements} on $In_xGa_{1-x}As$ NWs, in a home built measurement setup. The device of interest is fabricated with the help of Electron Beam Lithography (EBL) and a novel method of \textbf{selective area regrowth}. The pattern is made with the help of Hydrogen Silesquixone (HSQ) negative tone E-beam resist on a semi-insulating InP substrate. The device geometry allows placement of probe electrodes exactly opposite to each other, which is very important to extract Hall voltage and hence the mobility of the NW. Ti/Pd and Au bilayer is used to make the contact pads which are again defined by EBL with PMMA positive E-beam resist. The samples were mounted on an insulating ceramic holder and each device was manually wire bonded to the contact pins using a 0.25 \textmu m gauge aluminium wire. And Hall measurements were performed on the successful devices at room temperature. For the proposed geometry, the devices exhibited electron mobility values $\approx (5000 \pm 800)$ cm$^2$/Vs.Co-founder of Intel Corp, Gordon Moore made a very famous observation in 1965 about shrinking integrated circuits. During that time, portable computers and other handheld devices were yet to be common place objects. Computers consumed lot of power and consequently produced lot of heat. They were also very expensive, mainly due to the cost involved in making them. Moore’s prediction which is popularly called ‘Moore’s Law’, made a statement which predicted that the semiconductor industries will squeeze twice as many transistors on a silicon chip in 10 years. This meant faster computers for same or lower cost. Later in 1975, the time span of the prediction was updated to 2 years. Now, major semiconductor industries are shrinking the transistor size and cost every two years, to make computers and other wireless devices faster and affordable than ever. But, this trend won’t continue forever. We can’t shrink the size of the transistor beyond certain node. This will cripple the semiconductor industry and they won’t be able to satisfy out ever growing huger for computing power. To deliver what is expected from them, they have started looking for alternative, innovative ideas to increase computing speed and reduce cost. And my work is to about developing such innovative ideas. Silicon chips no longer offer space to squeeze more transistors, it is time for us to move to other semiconductors like Indium Gallium Arsenide(InGaAs). Electrons move much faster in InGaAs than in normal silicon transistors. It is an established fact that the electrons move faster in InGaAs, in their bulk. But, transistor sizes have already reduced down to billionth of a meter in 2013. In order to make relevant innovation, one should properly understand how InGaAs will act in such dimensions. But, there are very few reports about that. In my work, I have developed a special manufacturing process, which will allow one to fabricate InGaAs in the form of a nanowire. The nanowires were only 50 nm in their width and 2 – 3 μm in their length. In order to analyze how fast electrons travel in the nanowire, hall measurements should be performed on them. Hall Effect is commonly used in semiconductors to find how fast the charge carriers are travelling in them. In order to perform hall measurement on the nanowire, I have developed a special design which will make the measurement easier and accurate. Initially, there was lot of problems in realizing the design for such small dimensions. But after lot of optimization, I succeeded in realizing the design and performed hall measurements. It was found that the electrons travel at a speed of ~5000 cm2/Vs in an InGaAs nanowire device. Though it was expected to be much higher, due to some current leakage the performance was poor. But, a reliable manufacturing process and a proper design was developed. In future, more accurate measurements can be made, so that we find alternative ways to shrink transistor size and cost

Review Of Compound Semiconductors Relieving Bottlenecks Of Incessant MOSFET Scaling: Heroism Or A Race In The Dark

In last five decades, the exponential demand in the field of electronic applications is powered by a drastic escalation in the compactness of silicon based complementary metal oxide semiconductor (CMOS) field effect transistor (FETs) and qugumentation in logical performance. But silicon based transistor scaling is now heading to its restraints, intimidating to cease the micro-electronics revolution. Another family of semiconductor materials thus have been under surveil- lance that can be rightly placed to handle this problem: Compound Semiconductors. The spectacular electron transport features of such materials might be point of focus that can lead to development of FETs based on such materials in nano-scale regime. This article provides a speculation in the future of compound semiconductor material-based devices with emphasis on effects of incessant scaling. Whilst aggressive scaling, requirements and constraints that include power dissipation, operating frequency, gain, leakage current must be kept balanced with predictive technologies nodes and also with the fabricating aspects of devices. The scaling restraints requisite a transformation from planar architectures to three-dimensional device structures to cater future performance requirements of CMOS nodes beyond 10 nm. Compound semiconductor materials are progressively waged in various electronic, opto-electronic, and photonic applications due to the prospects of adjusting the properties over a broad parameter domain conveniently by tuning the alloy composition. Ironically, the material properties are also willed by the atomic-scale orientation of compound semiconductors in sub-nanometer scale. Compound semiconductors FET based logic circuits perform 5 folds faster than similar topology circuits based on silicon, whilst dissipating only half of the power. Here a comprehensive review is presented that outlines how compound semiconductor materials mitigate various effects of aggressive scaling in nanometer scale and the adjoining effects

InGaAs Nanowire and Quantum Well Devices

To fulfill the increasing demand for high-speed electronics used for computation or communication is one everlasting challenge for the semiconductor industry. Emerging fields such as quantum computation also has a need for circuits operating at cryogenic temperatures. The metal-oxide-semiconductor field-effect transistor (MOSFET) is the main component in modern electronics, traditionally fabricated in Si. However, III-V materials generally exhibits higher electron mobility compared to Si. This enables the realization of MOSFETs with higher operational speed or lower power consumption. While a nanowire geometry, where the channel is gated from multiple sides brings an increase in the electrostatic gate control, allowing for further gate length scaling. In this thesis, lateral InGaAs nanowire and quantum well devices have been fabricated and characterized with the purpose of understanding the electron transport and its limitations over a wide temperature range. MOSFETs at cryogenic temperatures, where the phonon occupation is low, are highly sensitive to disorder and defects in the semiconductor/oxide interface. InGaAs RF MOSFETs with different spacer technologies for reducing capacitances have also been fabricated and characterized. Optimizing the spacers for low capacitance and low access resistance is a key design consideration when fabricating devices for high-frequency operation