Power-aware partitioning of data converters

Serial data streaming, one of the most important functions in modern communication systems, is becoming more and more power consuming as bit-rate is increasing without standstill. In this work, we propose a novel technique for partitioning conventional N-bit registers in standard data converters, in order to reduce their switching activity, and therefore power consumption. The architecture here presented have a very low area overhead with respect to the standard ones for serializers and, furthermore, it allows different (i.e., custom) configurations for the partitioning. The proposed method even allows to extract idleness conditions of register banks in order to apply the well-known clock-gating technique to the circuit and thus furtherly reducing the total power consumption. This method has been applied to different data converters (i.e., serializers) in a base-band radio within an ultra low-power industrial design and the results highlight the effectiveness of the proposed techniqu