Heurísticas bioinspiradas para el problema de Floorplanning 3D térmico de dispositivos MPSoCs

Tesis inédita de la Universidad Complutense de Madrid, Facultad de Informática, Departamento de Arquitectura de Computadores y Automática, leída el 20-06-2013Depto. de Arquitectura de Computadores y AutomáticaFac. de InformáticaTRUEunpu

Graphics Processing Unit-Based Computer-Aided Design Algorithms for Electronic Design Automation

The electronic design automation (EDA) tools are a specific set of software that play important roles in modern integrated circuit (IC) design. These software automate the design processes of IC with various stages. Among these stages, two important EDA design tools are the focus of this research: floorplanning and global routing. Specifically, the goal of this study is to parallelize these two tools such that their execution time can be significantly shortened on modern multi-core and graphics processing unit (GPU) architectures. The GPU hardware is a massively parallel architecture, enabling thousands of independent threads to execute concurrently. Although a small set of EDA tools can benefit from using GPU to accelerate their speed, most algorithms in this field are designed with the single-core paradigm in mind. The floorplanning and global routing algorithms are among the latter, and difficult to render any speedup on the GPU due to their inherent sequential nature. This work parallelizes the floorplanning and global routing algorithm through a novel approach and results in significant speedups for both tools implemented on the GPU hardware. Specifically, with a complete overhaul of solution space and design space exploration, a GPU-based floorplanning algorithm is able to render 4-166X speedup, while achieving similar or improved solutions compared with the sequential algorithm. The GPU-based global routing algorithm is shown to achieve significant speedup against existing state-of-the-art routers, while delivering competitive solution quality. Importantly, this parallel model for global routing renders a stable solution that is independent from the level of parallelism. In summary, this research has shown that through a design paradigm overhaul, sequential algorithms can also benefit from the massively parallel architecture. The findings of this study have a positive impact on the efficiency and design quality of modern EDA design flow

Proceedings of the 5th International Workshop on Reconfigurable Communication-centric Systems on Chip 2010 - ReCoSoC\u2710 - May 17-19, 2010 Karlsruhe, Germany. (KIT Scientific Reports ; 7551)

ReCoSoC is intended to be a periodic annual meeting to expose and discuss gathered expertise as well as state of the art research around SoC related topics through plenary invited papers and posters. The workshop aims to provide a prospective view of tomorrow\u27s challenges in the multibillion transistor era, taking into account the emerging techniques and architectures exploring the synergy between flexible on-chip communication and system reconfigurability

Optimización térmica del banco de registros mediante técnicas de computación evolutiva y simulación de eventos discretos

El procesador MIPS es utilizado en cursos de arquitectura de computadores para explicar materias tales como análisis de rendimiento, consumo de energía o fiabilidad. Por otro lado, el formalismo DEVS es un acrónimo del inglés para referirse a Discrete Event System Specification, o lo que es lo mismo Especificación de Sistemas de Eventos Discretos. El término es ahora estándar en el campo de la simulación para referirse a un formalismo modular y jerárquico, muy utilizado para modelar y analizar sistemas de diversos tipos. En la actualidad, ya que cada vez se desean obtener computadoras más potentes, es interesante conocer de qué manera se pueden redistribuir ciertos componentes de modo que el calor desprendido no sea excesivo y tal que el coste de enfriamiento no sea muy alto. En este proyecto se realiza un estudio térmico del modelo MIPS utilizando DEVS. Concretamente, por facilidad a la hora de obtener conclusiones y dado que se trata de un proyecto relativamente pequeño, desarrollamos una metodología que, mediante políticas de reasignación de registros basadas en algoritmos genéticos, disminuya considerablemente la temperatura final del Banco de Registros. [ABSTRACT] The MIPS processor is used in computer architecture courses in order to explain matters such as performance analysis, energy consumption or reliability. On the other hand, DEVS is a formalism used for modeling and analyzing discrete event systems. This is a standard term in the field of simulation referring to a modular and hierarchical formalism that is very used to model and analyze many different systems. Nowadays, due to the desire for more powerful computers, it is interesting to learn how to reallocate certain components in order to achieve heat reduction, with low cooling costs. In this project we carry out a thermal analysis of the MIPS processor using DEVS. Specifically, because this is simpler if we intend to draw conclusions and because this is a relatively small project, we develop a methodology which, through register reallocation policy based on genetic algorithms, notably decreases the resulting Register Bank temperature