Power Optimization of Delay Constrained CMOS Bus Drivers

The design automation of minimum power delayconstrained CMOS Bus Drivers for library-based (standardcells) and full-custom design environments is presented in this paper. The effect of the short circuit current consumption is taken into account in the total power evaluation. The proposed methodology is applied to efficiently find the optimum selection of buffers for any given bus load and delay constraint. Comparisons with other strategies, such as constant taper or minimum power-delay solutions, show power savings of more than 100% using the proposed methodology. Analytical predictions and results show good agreement with time costly SPICE simulations and reflect the need of variable taper factors for low power buffers in synchronous CMOS digital circuits. 1 Introduction The ever growing demand for highly portable electronic devices, together with the appearance of serious heat dissipation problems, has raised an urgent need to approach the design of lowpower CMOS circuitry. Moreove..