On track for solar grade silicon through a Siemens process-type laboratory reactor: operating conditions and energy savings

Polysilicon cost impacts significantly on the photovoltaics (PV) cost and on the energy payback time. Nowadays, the besetting production process is the so called Siemens process, polysilicon deposition by chemical vapor deposition (CVD) from Trichlorosilane. Polysilicon purification level for PV is to a certain extent less demanding that for microelectronics. At the Instituto de Energía Solar (IES) research on this subject is performed through a Siemens process-type laboratory reactor. Through the laboratory CVD prototype at the IES laboratories, valuable information about the phenomena involved in the polysilicon deposition process and the operating conditions is obtained. Polysilicon deposition by CVD is a complex process due to the big number of parameters involved. A study on the influence of temperature and inlet gas mixture composition on the polysilicon deposition growth rate, based on experimental experience, is shown. Moreover, CVD process accounts for the largest contribution to the energy consumption of the polysilicon production. In addition, radiation phenomenon is the major responsible for low energetic efficiency of the whole process. This work presents a model of radiation heat loss, and the theoretical calculations are confirmed experimentally through a prototype reactor at our disposal, yielding a valuable know-how for energy consumption reduction at industrial Siemens reactorsPostprint (published version

Fabrication of an active nanostencil with integrated microshutters

An active nanostencil, consisting of a thin (200 nm) silicon nitride membrane with attached polysilicon microactuators that can be used to dynamically open and/or close holes in the silicon nitride membrane, is presented. This nanostencil can be used as a shadow mask in an evaporation setup. Main features of the nanostencil are the absence of sacrificial oxide in the final product, strengthening of the membrane by a polysilicon hexagonal structure that is attached directly to the membrane and the use of low-doped regions in the polysilicon to separate the stator and rotor electrically

Analysis of the high-speed polysilicon photodetector in fully standard CMOS technology

A high-performance lateral polysilicon photodiode was designed in standard 0.18 um CMOS technology. The device has a frequency bandwidth far in the GHz range: the measured bandwidth of the poly photodiode was 6 GHz, which gure was limited by the measurement equipment. The high intrinsic (physical) bandwidth is due to a short excess carrier lifetime. The external (electrical) bandwidth is also high because of a very small parasitic capacitance (<0.1 pF). This is the best bandwidth performance among all reported diodes designed in a standard CMOS. The quantum efficiency of this poly photodiode is 0.2% due to the very small light sensitive diode volume. The diode active area is limited by a narrow depletion region and its depth by the technology

Surface micromachined mechanisms and micromotors

Electric micromotors are sub-millimeter sized actuators capable of unrestrained motion in at least one degree of freedom. Polysilicon surface micromachining using heavily phosphorus-doped LPCVD polysilicon for the structural material, LPCVD silicon nitride for the electrical isolation and deposited silicon dioxide for the sacrificial material has formed the fabrication technology base for the development of these micromotors. Two polysilicon surface micromachining processes, referred to here as the center-pin and flange, have been demonstrated for the fabrication of passive mechanisms and micromotors. Passive mechanisms such as gear trains, cranks and manipulators have been implemented on silicon. Reported operational micromotors have been of the rotary variable-capacitance salient-pole and harmonic (or wobble) side-drive designs. These micromotors are capable of motive torques in the 10 pN m order of magnitude range. Preliminary progress has been made in studying the operational, friction and wear characteristics of these micromechanical devices. Typical operational voltages have been as low as 37 V and 26 V across 1.5 mu m air gap salient-pole and harmonic micromotors. These excitations correspond to electric field intensities above 10(8) Vm-1 in the micromotor air gaps. Salient-pole and wobble micromotors have been reported to operate at speeds as high as 15000 rpm and 700 rpm, respectively. Micromotor lifetimes of at least many millions of cycles over a period of several days have been reported

MEMS flow sensors for nano-fluidic applications

This paper presents micromachined thermal sensors for measuring liquid flow rates in the nanoliter-per-minute range. The sensors use a boron-doped polysilicon thinfilm heater that is embedded in the silicon nitride wall of a microchannel. The boron doping is chosen to increase the heater’s temperature coefficient of resistance within tolerable noise limits, and the microchannel is suspended from the substrate to improve thermal isolation. The sensors have demonstrated a flow rate resolution below 10 nL/min, as well as the capability for detecting micro bubbles in the liquid. Heat transfer simulation has also been performed to explain the sensor operation and yielded good agreement with experimental data

Integrated movable micromechanical structures for sensors and actuators

Movable pin-joints, gears, springs, cranks, and slider structures with dimensions measured in micrometers have been fabricated using silicon microfabrication technology. These micromechanical structures, which have important transducer applications, are batch-fabricated with an IC-compatible process. The movable mechanical elements are built on layers that are later removed so that they are freed for translation and rotation. An undercut-and-refill technique, which makes use of the high surface mobility of silicon atoms undergoing chemical vapor deposition, is used to refill undercut regions in order to form restraining flanges. Typical element sizes and masses are measured in micrometers and nanograms. The process provides the tiny structures in an assembled form avoiding the nearly impossible challenge of handling such small elements individually

An Electrically Programmable Split-Electrode Charge-Coupled Transversal Filter (EPSEF)

A CCD split-electrode transversal filter (EPSEF) with analog controlled tap weights is described. The programmable tap weighting utilizes a novel analog multiplier for sampled data, based on charge profiling underneath a resistive gate structure. The EPSEF device concept and the performance data of a prototype filter with eight programmable taps are presented. Applications of the EPSEF in several programmed filter functions and in an adaptive filter system are demonstrated

Fabrication of Surface Micromachined AlN Piezoelectric Microstructures and its Potential Apllication to RF Resonators

We report on a novel microfabrication method to fabricate aluminum nitride (AlN) piezoelectric microstructures down to 2 microns size by a surface micromachining process. Highly c-axis oriented AlN thin films are deposited between thin Cr electrodes on polysilicon structural layers by rf reactive sputtering. The top Cr layer is used both as a mask to etch the AlN thin films and as an electrode to actuate the AlN piezoelectric layer. The AlN layer is patterned anisotropically by wet etching using a TMAH (25%) solution. This multilayer stack uses silicon-di-oxide as a sacrificial layer to make free-standing structures. One-port scattering paramenter measurement using a network analyzer show a resonant frequency of 1.781 GHz on a clamped-clamped beam suspended structure. The effective electromechanical coupling factor is calculated as 2.4 % and the measured bandwidth is 13.5 MHz for one such a doubly clamped beam (990x30) μm2

Sealing of micromachined cavities using chemical vapor deposition methods: characterization and optimization

This paper presents results of a systematic investigation to characterize the sealing of micromachined cavities using chemical vapor deposition (CVD) methods. We have designed and fabricated a large number and variety of surface-micromachined test structures with different etch-channel dimensions. Each cavity is then subjected to a number of sequential CVD deposition steps with incremental thickness until the cavity is successfully sealed. At etch deposition interval, the sealing status of every test structure is experimentally obtained and the percentage of structures that are sealed is recorded. Four CVD sealing materials have been incorporated in our studies: LPCVD silicon nitride, LPCVD polycrystalline silicon (polysilicon), LPCVD phosphosilicate glass (PSG), and PECVD silicon nitride. The minimum CVD deposition thickness that is required to successfully seal a microstructure is obtained for the first time. For a typical Type-1 test structure that has eight etch channels-each 10 μm long, 4 μm wide, and 0.42 μm tall-the minimum required thickness (normalized with respect to the height of etch channels) is 0.67 for LPCVD silicon nitride, 0.62 for LPCVD polysilicon, 4.5 for LPCVD PSG, and 5.2 for PECVD nitride. LPCVD silicon nitride and polysilicon are the most efficient sealing materials. Sealing results with respect to etch-channel dimensions (length and width) are evaluated (within the range of current design). When LPCVD silicon nitride is used as the sealing material, test structures with the longest (38 μm) and widest (16 μm) etch channels exhibit the highest probability of sealing. Cavities with a reduced number of etch channels seal more easily. For LPCVD PSG sealing, on the other hand, the sealing performance improves with decreasing width but is not affected by length of etch channels

Enhancement mode double top gated MOS nanostructures with tunable lateral geometry

We present measurements of silicon (Si) metal-oxide-semiconductor (MOS) nanostructures that are fabricated using a process that facilitates essentially arbitrary gate geometries. Stable Coulomb blockade behavior free from the effects of parasitic dot formation is exhibited in several MOS quantum dots with an open lateral quantum dot geometry. Decreases in mobility and increases in charge defect densities (i.e. interface traps and fixed oxide charge) are measured for critical process steps, and we correlate low disorder behavior with a quantitative defect density. This work provides quantitative guidance that has not been previously established about defect densities for which Si quantum dots do not exhibit parasitic dot formation. These devices make use of a double-layer gate stack in which many regions, including the critical gate oxide, were fabricated in a fully-qualified CMOS facility.Comment: 11 pages, 6 figures, 3 tables, accepted for publication in Phys. Rev.