Automatic synthesis of analog layout : a survey

A review of recent research in the automatic synthesis of physical geometry for analog integrated circuits is presented. On introduction, an explanation of the difficulties involved in analog layout as opposed to digital layout is covered. Review of the literature then follows. Emphasis is placed on the exposition of general methods for addressing problems specific to analog layout, with the details of specific systems only being given when they surve to illustrate these methods well. The conclusion discusses problems remaining and offers a prediction as to how technology will evolve to solve them. It is argued that although progress has been and will continue to be made in the automation of analog IC layout, due to fundamental differences in the nature of analog IC design as opposed to digital design, it should not be expected that the level of automation of the former will reach that of the latter any time soon

Time-domain optimization of amplifiers based on distributed genetic algorithms

Thesis presented in partial fulfillment of the requirements for the degree of Doctor of Philosophy in the subject of Electrical and Computer EngineeringThe work presented in this thesis addresses the task of circuit optimization, helping the designer facing the high performance and high efficiency circuits demands of the market and technology evolution. A novel framework is introduced, based on time-domain analysis, genetic algorithm optimization, and distributed processing. The time-domain optimization methodology is based on the step response of the amplifier. The main advantage of this new time-domain methodology is that, when a given settling-error is reached within the desired settling-time, it is automatically guaranteed that the amplifier has enough open-loop gain, AOL, output-swing (OS), slew-rate (SR), closed loop bandwidth and closed loop stability. Thus, this simplification of the circuit‟s evaluation helps the optimization process to converge faster. The method used to calculate the step response expression of the circuit is based on the inverse Laplace transform applied to the transfer function, symbolically, multiplied by 1/s (which represents the unity input step). Furthermore, may be applied to transfer functions of circuits with unlimited number of zeros/poles, without approximation in order to keep accuracy. Thus, complex circuit, with several design/optimization degrees of freedom can also be considered. The expression of the step response, from the proposed methodology, is based on the DC bias operating point of the devices of the circuit. For this, complex and accurate device models (e.g. BSIM3v3) are integrated. During the optimization process, the time-domain evaluation of the amplifier is used by the genetic algorithm, in the classification of the genetic individuals. The time-domain evaluator is integrated into the developed optimization platform, as independent library, coded using C programming language. The genetic algorithms have demonstrated to be a good approach for optimization since they are flexible and independent from the optimization-objective. Different levels of abstraction can be optimized either system level or circuit level. Optimization of any new block is basically carried-out by simply providing additional configuration files, e.g. chromosome format, in text format; and the circuit library where the fitness value of each individual of the genetic algorithm is computed. Distributed processing is also employed to address the increasing processing time demanded by the complex circuit analysis, and the accurate models of the circuit devices. The communication by remote processing nodes is based on Message Passing interface (MPI). It is demonstrated that the distributed processing reduced the optimization run-time by more than one order of magnitude. Platform assessment is carried by several examples of two-stage amplifiers, which have been optimized and successfully used, embedded, in larger systems, such as data converters. A dedicated example of an inverter-based self-biased two-stage amplifier has been designed, laid-out and fabricated as a stand-alone circuit and experimentally evaluated. The measured results are a direct demonstration of the effectiveness of the proposed time-domain optimization methodology.Portuguese Foundation for the Science and Technology (FCT

Tensor Computation: A New Framework for High-Dimensional Problems in EDA

Many critical EDA problems suffer from the curse of dimensionality, i.e. the very fast-scaling computational burden produced by large number of parameters and/or unknown variables. This phenomenon may be caused by multiple spatial or temporal factors (e.g. 3-D field solvers discretizations and multi-rate circuit simulation), nonlinearity of devices and circuits, large number of design or optimization parameters (e.g. full-chip routing/placement and circuit sizing), or extensive process variations (e.g. variability/reliability analysis and design for manufacturability). The computational challenges generated by such high dimensional problems are generally hard to handle efficiently with traditional EDA core algorithms that are based on matrix and vector computation. This paper presents "tensor computation" as an alternative general framework for the development of efficient EDA algorithms and tools. A tensor is a high-dimensional generalization of a matrix and a vector, and is a natural choice for both storing and solving efficiently high-dimensional EDA problems. This paper gives a basic tutorial on tensors, demonstrates some recent examples of EDA applications (e.g., nonlinear circuit modeling and high-dimensional uncertainty quantification), and suggests further open EDA problems where the use of tensor computation could be of advantage.Comment: 14 figures. Accepted by IEEE Trans. CAD of Integrated Circuits and System

MOSFET zero-temperature-coefficient (ZTC) effect modeling anda analysis for low thermal sensitivity analog applications

Continuing scaling of Complementary Metal-Oxide-Semiconductor (CMOS) technologies brings more integration and consequently temperature variation has become more aggressive into a single die. Besides, depending on the application, room ambient temperature may also vary. Therefore, procedures to decrease thermal dependencies of eletronic circuit performances become an important issue to include in both digital and analog Integrated Circuits (IC) design flow. The main purpose of this thesis is to present a design methodology for a typical CMOS Analog design flow to make circuits as insensitivity as possible to temperature variation. MOSFET Zero Temperature Coefficient (ZTC) and Transconductance Zero Temperature Coefficient (GZTC) bias points are modeled to support it. These are used as reference to deliver a set of equations that explains to analog designers how temperature will change transistor operation and hence the analog circuit behavior. The special bias conditions are analyzed using a MOSFET model that is continuous from weak to strong inversion, and both are proven to occur always from moderate to strong inversion operation in any CMOS fabrication process. Some circuits are designed using proposed methodology: two new ZTC-based current references, two new ZTC-based voltage references and four classical Gm-C circuits biased at GZTC bias point (or defined here as GZTC-C filters). The first current reference is a Self-biased CMOS Current Reference (ZSBCR), which generates a current reference of 5 A. It is designed in an 180 nm process, operating with a supply voltage from 1.4V to 1.8 V and occupying around 0:010mm2 of silicon area. From circuit simulations the reference shows an effective temperature coefficient (TCeff ) of 15 ppm/oC from 45 to +85oC, and a fabrication process sensitivity of = = 4:5%, including average process and local mismatch. Simulated power supply sensitivity is estimated around 1%/V. The second proposed current reference is a Resistorless Self-Biased ZTC Switched Capacitor Current Reference (ZSCCR). It is also designed in an 180 nm process, resulting a reference current of 5.88 A under a supply voltage of 1.8 V, and occupying a silicon area around 0:010mm2. Results from circuit simulation show an TCeff of 60 ppm/oC from -45 to +85 oC and a power consumption of 63 W. The first proposed voltage reference is an EMI Resisting MOSFET-Only Voltage Reference (EMIVR), which generates a voltage reference of 395 mV. The circuit is designed in a 130 nm process, occupying around 0.0075 mm2 of silicon area while consuming just 10.3 W. Post-layout simulations present a TCeff of 146 ppm/oC, for a temperature range from 55 to +125oC. An EMI source of 4 dBm (1 Vpp amplitude) injected into the power supply of circuit, according to Direct Power Injection (DPI) specification results in a maximum DC Shift and Peak-to-Peak ripple of -1.7 % and 35.8m Vpp, respectively. The second proposed voltage reference is a 0.5V Schottky-based Voltage Reference (SBVR). It provides three voltage reference outputs, each one utilizing different threshold voltage MOSFETs (standard-VT , low-VT , and zero-VT ), all available in adopted 130 nm CMOS process. This design results in three different and very low reference voltages: 312, 237, and 51 mV, presenting a TCeff of 214, 372, and 953 ppm/oC in a temperature range from -55 to 125oC, respectively. It occupies around 0.014 mm2 of silicon area for a total power consumption of 5.9 W. Lastly, a few example Gm-C circuits are designed using GZTC technique: a single-ended resistor emulator, an impedance inverter, a first order and a second order filter. These circuits are simulated in a 130 nm CMOS commercial process, resulting improved thermal stability in the main performance parameters, in the range from 27 to 53 ppm/°C.A contínua miniaturização das tecnologias CMOS oferece maior capacidade de integração e, consequentemente, as variações de temperatura dentro de uma pastilha de silício têm se apresentado cada vez mais agressivas. Ademais, dependendo da aplicação, a temperatura ambiente a qual o CHIP está inserido pode variar. Dessa maneira, procedimentos para diminuir o impacto dessas variações no desempenho do circuito são imprescindíveis. Tais métodos devem ser incluídos em ambos fluxos de projeto CMOS, analógico e digital, de maneira que o desempenho do sistema se mantenha estável quando a temperatura oscilar. A ideia principal desta dissertação é propor uma metodologia de projeto CMOS analógico que possibilite circuitos com baixa dependência térmica. Como base fundamental desta metodologia, o efeito de coeficiente térmico nulo no ponto de polarização da corrente de dreno (ZTC) e da transcondutância (GZTC) do MOSFET são analisados e modelados. Tal modelamento é responsável por entregar ao projetista analógico um conjunto de equações que esclarecem como a temperatura influencia o comportamento do transistor e, portanto, o comportamento do circuito. Essas condições especiais de polarização são analisadas usando um modelo de MOSFET que é contínuo da inversão fraca para forte. Além disso, é mostrado que as duas condições ocorrem em inversão moderada para forte em qualquer processo CMOS. Algumas aplicações são projetadas usando a metodologia proposta: duas referências de corrente baseadas em ZTC, duas referências de tensão baseadas em ZTC, e quatro circuitos gm-C polarizados em GZTC. A primeira referência de corrente é uma Corrente de Referência CMOS Auto-Polarizada (ZSBCR), que gera uma referência de 5uA. Projetada em CMOS 180 nm, a referência opera com uma tensão de alimentação de 1.4 à 1.8 V, ocupando uma área em torno de 0:010mm2. Segundo as simulações, o circuito apresenta um coeficiente de temperatura efetivo (TCeff ) de 15 ppm/oC para -45 à +85 oC e uma sensibilidade à variação de processo de = = 4:5% incluindo efeitos de variabilidade dos tipos processo e descasamento local. A sensibilidade de linha encontrada nas simulações é de 1%=V . A segunda referência de corrente proposta é uma Corrente de Referência Sem Resistor Auto-Polarizada com Capacitor Chaveado (ZSCCR). O circuito é projetado também em 180 nm, resultando em uma corrente de referência de 5.88 A, para uma tensão de alimentação de 1.8 V, e ocupando uma área de 0:010mm2. Resultados de simulações mostram um TCeff de 60 ppm/oC para um intervalo de temperatura de -45 à +85 oC e um consumo de potência de 63 W. A primeira referência de tensão proposta é uma Referência de Tensão resistente à pertubações eletromagnéticas contendo apenas MOSFETs (EMIVR), a qual gera um valor de referência de 395 mV. O circuito é projetado no processo CMOS 130 nm, ocupando em torno de 0.0075 mm2 de área de silício, e consumindo apenas 10.3 W. Simulações pós-leiaute apresentam um TCeff de 146 ppm/oC, para um intervalo de temperatura de 55 à +125oC. Uma fonte EMI de 4 dBm (1 Vpp de amplitude) aplicada na alimentação do circuito, de acordo com o padrão Direct Power Injection (DPI), resulta em um máximo de desvio DC e ondulação Pico-à-Pico de -1.7 % e 35.8m Vpp, respectivamente. A segunda referência de tensão é uma Tensão de Referência baseada em diodo Schottky com 0.5V de alimentação (SBVR). Ela gera três saídas, cada uma utilizando MOSFETs com diferentes tensões de limiar (standard-VT , low-VT , e zero-VT ). Todos disponíveis no processo adotado CMOS 130 nm. Este projeto resulta em três diferentes voltages de referências: 312, 237, e 51 mV, apresentando um TCeff de 214, 372, e 953 ppm/oC no intervalo de temperatura de -55 à 125oC, respectivamente. O circuito ocupa em torno de 0.014 mm2, consumindo um total de 5.9 W. Por último, circuitos gm-C são projetados usando o conceito GZTC: um emulador de resistor, um inversor de impedância, um filtro de primeira ordem e um filtro de segunda ordem. Os circuitos também são simulados no processo CMOS 130 nm, resultando em uma melhora na estabilidade térmica dos seus principais parâmetros, indo de 27 à 53 ppm/°C

Low-power switched capacitor voltage reference

Low-power analog design represents a developing technological trend as it emerges from a rather limited range of applications to a much wider arena affecting mainstream market segments. It especially affects portable electronics with respect to battery life, performance, and physical size. Meanwhile, low-power analog design enables technologies such as sensor networks and RFID. Research opportunities abound to exploit the potential of low power analog design, apply low-power to established fields, and explore new applications. The goal of this effort is to design a low-power reference circuit that delivers an accurate reference with very minimal power consumption. The circuit and device level low-power design techniques are suitable for a wide range of applications. To meet this goal, switched capacitor bandgap architecture was chosen. It is the most suitable for developing a systematic, and groundup, low-power design approach. In addition, the low-power analog cell library developed would facilitate building a more complex low-power system. A low-power switched capacitor bandgap was designed, fabricated, and fully tested. The bandgap generates a stable 0.6-V reference voltage, in both the discrete-time and continuous-time domain. The system was thoroughly tested and individual building blocks were characterized. The reference voltage is temperature stable, with less than a 100 ppm/°C drift, over a --60 dB power supply rejection, and below a 1 [Mu]A total supply current (excluding optional track-and-hold). Besides using it as a voltage reference, potential applications are also described using derivatives of this switched capacitor bandgap, specifically supply supervisory and on-chip thermal regulation

34th Midwest Symposium on Circuits and Systems-Final Program

Organized by the Naval Postgraduate School Monterey California. Cosponsored by the IEEE Circuits and Systems Society. Symposium Organizing Committee: General Chairman-Sherif Michael, Technical Program-Roberto Cristi, Publications-Michael Soderstrand, Special Sessions- Charles W. Therrien, Publicity: Jeffrey Burl, Finance: Ralph Hippenstiel, and Local Arrangements: Barbara Cristi

High-Performance Fpaa Design For Hierarchical Implementation Of Analog And Mixed-Signal Systems

The design complexity of today's IC has increased dramatically due to the high integration allowed by advanced CMOS VLSI process. A key to manage the increased design complexity while meeting the shortening time-to-market is design automation. In digital world, the field-programmable gate arrays (FPGAs) have evolved to play a very important role by providing ASIC-compatible design methodologies that include design-for-testability, design optimization and rapid prototyping. On the analog side, the drive towards shorter design cycles has demanded the development of high performance analog circuits that are configurable and suitable for CAD methodologies. Field-programmable analog arrays (FPAAs) are intended to achieve the benefits for analog system design as FPGAs have in the digital field. Despite of the obvious advantages of hierarchical analog design, namely short time-to-market and low non-recurring engineering (NRE) costs, this approach has some apparent disadvantages. The redundant devices and routing resources for programmability requires extra chip area, while switch and interconnect parasitics cause considerable performance degradation. To deliver a high-performance FPAA, effective methodologies must be developed to minimize those adversary effects. In this dissertation, three important aspects in the FPAA design are studied to achieve that goal: the programming technology, the configurable analog block (CAB) design and the routing architecture design. Enabled by the Laser MakelinkTM technology, which provides nearly ideal programmable switches, channel segmentation algorithms are developed to improve channel routability and reduce interconnect parasitics. Segmented routing are studied and performance metrics accounting for interconnect parasitics are proposed for performance-driven analog routing. For large scale arrays, buffer insertions are considered to further reduce interconnection delay and cross-coupling noise. A high-performance, highly flexible CAB is developed to realized both continuous-mode and switched-capacitor circuits. In the end, the implementation of an 8-bit, 50MSPS pipelined A/D converter using the proposed FPAA is presented as an example of the hierarchical analog design approach, with its key performance specifications discussed

NASA SERC 1990 Symposium on VLSI Design

This document contains papers presented at the first annual NASA Symposium on VLSI Design. NASA's involvement in this event demonstrates a need for research and development in high performance computing. High performance computing addresses problems faced by the scientific and industrial communities. High performance computing is needed in: (1) real-time manipulation of large data sets; (2) advanced systems control of spacecraft; (3) digital data transmission, error correction, and image compression; and (4) expert system control of spacecraft. Clearly, a valuable technology in meeting these needs is Very Large Scale Integration (VLSI). This conference addresses the following issues in VLSI design: (1) system architectures; (2) electronics; (3) algorithms; and (4) CAD tools

In-Body Energy Harvesting Power Management Interface for Post Heart Transplantation Monitoring

Deep tissue energy harvesters are of increasing interest in the development of battery-less implantable devices. This paper presents a fully integrated ultra-low quiescent power management interface. It has power optimization and impedance matching between a piezoelectric energy harvester and the functional load that could be potentially powered by the heart's mechanical motions. The circuit has been designed in 0.18-µm CMOS technology. It dissipates 189.8 nW providing two voltage outputs of 1.4 V and 4.2 V. The simulation results show an output power 8.2x times of an ideal full-bridge rectifier without an external power supply. The design has the potential for use in self-powered heart implantable devices as it is capable providing stable output voltages from a cold startup