Symmetric Interconnection Networks from Cubic Crystal Lattices

Torus networks of moderate degree have been widely used in the supercomputer industry. Tori are superb when used for executing applications that require near-neighbor communications. Nevertheless, they are not so good when dealing with global communications. Hence, typical 3D implementations have evolved to 5D networks, among other reasons, to reduce network distances. Most of these big systems are mixed-radix tori which are not the best option for minimizing distances and efficiently using network resources. This paper is focused on improving the topological properties of these networks. By using integral matrices to deal with Cayley graphs over Abelian groups, we have been able to propose and analyze a family of high-dimensional grid-based interconnection networks. As they are built over $n$-dimensional grids that induce a regular tiling of the space, these topologies have been denoted \textsl{lattice graphs}. We will focus on cubic crystal lattices for modeling symmetric 3D networks. Other higher dimensional networks can be composed over these graphs, as illustrated in this research. Easy network partitioning can also take advantage of this network composition operation. Minimal routing algorithms are also provided for these new topologies. Finally, some practical issues such as implementability and preliminary performance evaluations have been addressed

Statistical approach to NoC design

Chip multiprocessors (CMPs) combine increasingly many general-purpose processor cores on a single chip. These cores run several tasks with unpredictable communication needs, resulting in uncertain and often-changing traffic patterns. This unpredictability leads network-on-chip (NoC) designers to plan for the worst-case traffic patterns, and significantly over-provision link capacities. In this paper, we provide NoC designers with an alternative statistical approach. We first present the traffic-load distribution plots (T-Plots), illustrating how much capacity over-provisioning is needed to service 90%, 99%, or 100% of all traffic patterns. We prove that in the general case, plotting T-Plots is #P-complete, and therefore extremely complex. We then show how to determine the exact mean and variance of the traffic load on any edge, and use these to provide Gaussian-based models for the T-Plots, as well as guaranteed performance bounds. Finally, we use T-Plots to reduce the network power consumption by providing an efficient capacity allocation algorithm with predictable performance guarantees. © 2008 IEEE

Reliability-aware multi-segmented bus architecture for photonic networks-on-chip

Network-on-chip (NoC) has emerged as an enabling platform for connecting hundreds of cores on a single chip, allowing for a structured, scalable system when compared to traditional on-chip buses. However, the multi-hop wireline paths in traditional NoCs result in high latency and energy dissipation causing an overall degradation in performance, especially for increasing system size. To alleviate this problem a few radically different interconnect technologies are envisioned. One such method of interconnecting different cores in NoCs is photonic interconnects. Photonic NoCs are on-chip communications networks in which information is transmitted in the form of optical signals. Photonic interconnection is one of the leading examples of emerging technology for on-chip interconnects. Existing innovative photonic NoC architectures have improved performance and reduced energy dissipation. Most architectures use Wavelength Division Multiplexing (WDM) on the photonic waveguides to increase the data bandwidth. However they have issues relating to reliability, such as waveguide losses and adjacent channel crosstalk. These phenomena could have a crippling effect on a system, and most current architectures do not address these effects. A newly proposed topology, known as the Multiple-Segmented Bus topology, or MSB, has shown promise for solving, or at least reducing, many of the problems plaguing the design of photonic networks using a modification of a folded torus to transmit different wavelength signals simultaneously. The MSB segments the waveguides into smaller parts to limit the waveguide losses. The formal performance evaluation of this proposed architecture has not been completed. This thesis will analyze the performance of such a network when implemented as a NoC in terms of data bandwidth, energy dissipation, latency, and reliability. By analyzing and comparing performance, energy dissipations, and reliability, the MSB-based photonic NoC (MSB-PNoC) can be compared to other state-of-the-art photonic NoCs to determine the feasibility of this topology for future network-on-chip designs