하이브리드 메모리 구조에서 접근 패턴에 기반한 페이지 배치 알고리즘

학위논문 (석사)-- 서울대학교 대학원 공과대학 컴퓨터공학부, 2017. 8. 엄현상.Due to the high memory footprint pressure, the hybrid memory architecture consisting of small-sized DRAM and large-sized PCM has been regarded as a promising approach. This architecture aims at (1) alleviating the high power consumption caused by large-sized DRAM, and (2) harnessing the non-volatility and in-place update capability of PCM. Numerous studies have addressed the importance of page placement scheme between two different types of memory frames. Particularly, they have made every effort to provide good wear-leveling, hide the low write speed of PCM and reduce the power consumption. However, they lack one of the two points: (1) read-dominated workloads also decrease the system-wide energy efficiency and (2) excessive page migration should be avoided. In order to solve the abovementioned problems, we propose an access-pattern- aware page placement algorithm. Fundamentally, it uses page-leveling policy using multi-queue. To set the level of a page, it uses weighted access counting which puts a more emphasis on write accesses without ignoring read accesses. To minimize the number of migrations from DRAM to PCM, it performs state-transition-based recency checking for pages in DRAM. Our experimental results clearly demonstrate that it can reduce the average memory access time by up to 39% and the power consumption by up to 57%, respectively, compared to the previous approaches. Furthermore, they show that the PCM wear-out performance can be improved by 27%.Chapter 1 Introduction 1 Chapter 2 Background and Motivation 6 2.1 Memory Architecture with DRAM and NVRAM 6 2.2 Motivating Examples 8 Chapter 3 Solution 12 3.1 Overview 12 3.2 Page Leveling 15 3.3 Getting a Free Page Frame from DRAM 18 3.4 Recency Checking 21 Chapter 4 Experimental Evaluation 26 4.1 Experimental Setup 26 4.2 Effect of Recency Checking 31 4.3 Effect of page placement algorithm depending on w-based access frequency 33 4.3.1 Effect on the number of page migrations 34 4.3.2 Effect on the average memory access time and the power consumption 35 4.3.3 Effect on the Lifetime of PCM 39 4.4 Performance analysis performed while varying the DRAM size 40 4.5 Techniques for further performance improvements 43 Chapter 5 Related Work 49 Chapter 6 Conclusion 52 Bibliography 54 초록 57Maste