Comparison analysis on scaling the vertical and lateral NMOSFET in nanometer regime

Conventional lateral and vertical n-channel MOS transistors with channel length in the range of 100 nm to 50 nm have been systematically investigated by means of device simulation. The comparison analysis includes critical parameters that govern device performance. Threshold voltage VT roll-off, leakage current Ioff drain saturation current IDsat and sub-threshold swing S were analyze and compared between the device. Due to double gate (DG) structure over the side of silicon pillar a better electrostatics potential control of channel is obtained in vertical device shown by an analysis on VT roll-off. A two decade higher of Ioff in planar device is observed with Lg = 50 nm. A factor of three times larger IDsat is observed for vertical MOSFETs compared to planar device. The sub-threshold swing S remains almost the same when the Lg larger than 80 nm. It increased rapidly when the Lg is scaled down to 50 nm due to the short channel effect SCE. However, the vertical device has a steady increase whereas the planar device has suffered immediate enhance of SCE. The analysis results confirmed that vertical MOSFET with double-gate structure is a potential solution to overcome SCE when scaled the channel length to 50 nm and beyond

Implementation of Taguchi Method for Lower Drain Induced Barrier Lowering in Vertical Double Gate NMOS Device

This paper presents a study in which an attempt has been made to reduce the drain induced barrier lowering (DIBL) in Vertical Double Gate NMOS device by optimizing multiple process parameter using L12 orthogonal array of Taguchi method. The device performance depended on the amount of DIBL effects that were successfully suppressed in the device. The Taguchi method comprised an orthogonal array (OA), main effects, signal-to-noise ratio (SNR) and analysis of variance (ANOVA) which were employed to analyze the effects of multiple process parameters on the DIBL of the device. Analysis of the experimental results revealed that the halo implant tilt angle was the most dominant process parameter which had a major influence on DIBL value with 62% of factor effect on SNR. Meanwhile, the lowest possible DIBL value retrieved after the optimization approach was observed to be 43.97 mV/V

Application Of Taguchi Method With The Interaction Test For Lower DIBL IN WSix/TiO2 Channel Vertical Double Gate NMOS

The poly-Si/SiO2 based MOSFETs have been encountering a problem with the limitation of channel length for the device miniaturization. The drain induced barrier lowering (DIBL) effect is the main threat for the device to acquire excellent device’s characteristics. Thus, the metal-gate/high-k technology is a smart choice for the future replacement of poly-Si/SiO2 channel. This paper introduces the implementation of WSix/TiO2 channel to replace the poly-Si/SiO2 channel in vertical double-gate NMOS structure, followed by the application of Taguchi method to reduce the drain induced barrier lowering (DIBL) effects. The device was virtually fabricated and characterized by using both ATHENA and ATLAS modules of SILVACO TCAD tools. The L12 orthogonal array, main effects, signal-to noise ratio (SNR) and analysis of variance (ANOVA) were utilized to analyze the effect of process parameter variations on the DIBL. Later, the interactions between the process parameters were investigated by using L8 orthogonal array of Taguchi method. Based on the final results, halo implant tilt angle and source/drain (S/D) implant energy were identified as the most dominant process parameters where each of them contributes 24% and 16% of factor effects on SNR respectively. The lowest possible value of DIBL after the optimization with the interaction test is 1.552 mV/V