TISCC: A Surface Code Compiler and Resource Estimator for Trapped-Ion Processors

We introduce the Trapped-Ion Surface Code Compiler (TISCC), a software tool that generates circuits for a universal set of surface code patch operations in terms of a native trapped-ion gate set. To accomplish this, TISCC manages an internal representation of a trapped-ion system where a repeating pattern of trapping zones and junctions is arranged in an arbitrarily large rectangular grid. Surface code operations are compiled by instantiating surface code patches on the grid and using methods to generate transversal operations over data qubits, rounds of error correction over stabilizer plaquettes, and/or lattice surgery operations between neighboring patches. Beyond the implementation of a basic surface code instruction set, TISCC contains corner movement functionality and a patch translation that is implemented using ion movement alone. Except in the latter case, all TISCC functionality is extensible to alternative grid-like hardware architectures. TISCC output has been verified using the Oak Ridge Quasi-Clifford Simulator (ORQCS).Comment: 10 pages, 5 figures. Software to be released at https://github.com/ORNL-QCI/TISC

Control Requirements and Benchmarks for Quantum Error Correction

Reaching useful fault-tolerant quantum computation relies on successfully implementing quantum error correction (QEC). In QEC, quantum gates and measurements are performed to stabilize the computational qubits, and classical processing is used to convert the measurements into estimated logical Pauli frame updates or logical measurement results. While QEC research has concentrated on developing and evaluating QEC codes and decoding algorithms, specification and clarification of the requirements for the classical control system running QEC codes are lacking. Here, we elucidate the roles of the QEC control system, the necessity to implement low latency feed-forward quantum operations, and suggest near-term benchmarks that confront the classical bottlenecks for QEC quantum computation. These benchmarks are based on the latency between a measurement and the operation that depends on it and incorporate the different control aspects such as quantum-classical parallelization capabilities and decoding throughput. Using a dynamical system analysis, we show how the QEC control system latency performance determines the operation regime of a QEC circuit: latency divergence, where quantum calculations are unfeasible, classical-controller limited runtime, or quantum-operation limited runtime where the classical operations do not delay the quantum circuit. This analysis and the proposed benchmarks aim to allow the evaluation and development of QEC control systems toward their realization as a main component in fault-tolerant quantum computation.Comment: 21+9(SM) pages, 6+3(SM) figure

Real-Time Decoding for Fault-Tolerant Quantum Computing: Progress, Challenges and Outlook

Quantum computing is poised to solve practically useful problems which are computationally intractable for classical supercomputers. However, the current generation of quantum computers are limited by errors that may only partially be mitigated by developing higher-quality qubits. Quantum error correction (QEC) will thus be necessary to ensure fault tolerance. QEC protects the logical information by cyclically measuring syndrome information about the errors. An essential part of QEC is the decoder, which uses the syndrome to compute the likely effect of the errors on the logical degrees of freedom and provide a tentative correction. The decoder must be accurate, fast enough to keep pace with the QEC cycle (e.g., on a microsecond timescale for superconducting qubits) and with hard real-time system integration to support logical operations. As such, real-time decoding is essential to realize fault-tolerant quantum computing and to achieve quantum advantage. In this work, we highlight some of the key challenges facing the implementation of real-time decoders while providing a succinct summary of the progress to-date. Furthermore, we lay out our perspective for the future development and provide a possible roadmap for the field of real-time decoding in the next few years. As the quantum hardware is anticipated to scale up, this perspective article will provide a guidance for researchers, focusing on the most pressing issues in real-time decoding and facilitating the development of solutions across quantum and computer science

Pauli Frames for Quantum Computer Architectures

Quantum computers hold the promise to solve problems that are intractable to classical computers. Since qubits suffer from extremely short lifetime and unreliable operations, Quantum Error Correction (QEC) forms a vital part of a quantum computer to enable Fault-Tolerant quantum computing. The usage of a Pauli frame can relax the time constraints on QEC by keeping track of detected errors in classical logic. For the first time, in the background of a heterogeneous quantum computer architecture, we clarified the input/output and working principles of a Pauli frame, which can soon be mapped to a hardware implementation. We proposed the first functional quantum computer architecture simulation platform, QPDO, which can connect to different quantum simulators, such as QX Simulator or CHP, and is used to verify the logical operations of a Surface Code 17 (SC17) logical qubit. Finally, by using QPDO we found that a Pauli frame does not improve the Logical Error Rate (LER) of a SC17 logical qubit, which is opposite to previous understanding. By further reasoning, we also expect no improvement in LER by using a Pauli frame for surface codes with a larger distance. Nevertheless, the usage of a Pauli frame is still crucial for relaxing the timing constraints on QEC.Electrical Engineering, Mathematics and Computer ScienceComputer Engineerin