Partial Configuration Design and Implementation Challenges on Xilinx Virtex Fpgas

In this paper, we address the main aspects of partial reconfiguration on the Xilinx Virtex FPGAs and explain how to overcome main challenges during partial reconfiguration design and implementation, in specific about signal integrity, global logic and inter-module communication. In addition, we discuss the problem of designing partial reconfigurable application using the HandelC language, and illustrate this approach by using one example in video rendering