Reliable Hardware Architectures of CORDIC Algorithm with Fixed Angle of Rotations

Fixed-angle rotation operation of vectors is widely used in signal processing, graphics, and robotics. Various optimized coordinate rotation digital computer (CORDIC) designs have been proposed for uniform rotation of vectors through known and specified angles. Nevertheless, in the presence of faults, such hardware architectures are potentially vulnerable. In this thesis, we propose efficient error detection schemes for two fixed-angle rotation designs, i.e., the Interleaved Scaling and Cascaded Single-rotation CORDIC. To the best of our knowledge, this work is the first in providing reliable architectures for these variants of CORDIC. The former is suitable for low-area applications and, hence, we propose recomputing with encoded operands schemes which add negligible area overhead to the designs. Moreover, the proposed error detection schemes for the latter variant are optimized for efficient applications which hamper the performance of the architectures negligibly. We present three variants of recomputing with encoded operands to detect both transient and permanent faults, coupled with signature-based schemes. The overheads of the proposed designs are assessed through Xilinx FPGA implementations and their effectiveness is benchmarked through error simulations. The results give confidence for the proposed efficient architectures which can be tailored based on the reliability requirements and the overhead to be tolerated

High Energy Physics Division semiannual report of research activities, July 1, 1991--December 31, 1991

This report describes the research conducted in the High Energy Physics Division of Argonne National Laboratory during the period of July 1, 1991--December 31, 1991. Topics covered here include experimental and theoretical particle physics, advanced accelerator physics, detector development, and experimental facilities research. Lists of division publications and colloquia are included

Proton-Antiproton Annihilation and Meson Spectroscopy with the Crystal Barrel

This report reviews the achievements of the Crystal Barrel experiment at the Low Energy Antiproton Ring (LEAR) at CERN. During seven years of operation Crystal Barrel has collected very large statistical samples in pbarp annihilation, especially at rest and with emphasis on final states with high neutral multiplicity. The measured rates for annihilation into various two-body channels and for electromagnetic processes have been used to test simple models for the annihilation mechanism based on the quark internal structure of hadrons. From three-body annihilations three scalar mesons, a0(1450), f0(1370) and f0(1500) have been established in various decay modes. One of them, f0(1500), may be identified with the expected ground state scalar glueball.Comment: 64 pages, LATEX file, 36 figures are available as ps files at http://afuz01.cern.ch/claude/ Submitted to Reviews of Modern Physic

Prospects of Finding New Fundamental Physics and Upgrade Studies with the ATLAS detector at the LHC

This thesis presents the work done to develop and qualify the Pixel Data Transmission Chain of the Inner Tracker (ITk) of the ATLAS experiment. To meet High Luminosity - Large Hadron Collider (HL-LHC) conditions, the ATLAS Inner Detector will adopt an all-silicon tracker with high-speed, radiation-resistant data transmission, of which a key stage is the electrical-to-optical component called optoboard. The optoboard is the fundamental component of the optosystem, which is responsible for the recovery, aggregation and electrical-optical conversion of all ITk Pixel data links. This thesis describes the design of the optosystem and the key components of the ITk Pixel data transmission chain, namely, the GBCR which restores the data that is attenuated after electrical transmission from the modules, the lpGBT which multiplexes and de-multiplexes the outgoing and incoming signal and the VTRx+ which is responsible for the electrical-to-optical conversion using a 850 nm laser diode. Functionality tests were performed to validate the design of the optoboard and to analyse and qualify the signal over the electrical part of the ITk Pixel data transmission chain to ensure that the the transmitted data is not distorted or lost and the required specifications fulfilled. Overall, the ITk Pixel electrical data transmission chain from the pixel modules to the optoboard is able to satisfy the requirements of BER < 10−12 for a signal loss < 20 dB with lowest observed total jitter of ~ 110 ps. Furthermore, the Optosystem and the ITk Pixel Data Transmission Chain has successfully passed the final design review and is scheduled to be installed in ATLAS in the next long shutdown in 2026-2028. This thesis also documents the results of the analysis which searches for 3rd generation squarks with final states consisting of top and bottom quarks and missing transverse energy (Emiss/T ) using the ATLAS detector at the Large Hadron Collider (LHC). The Standard Model (SM) of Particle Physics accurately predicts observed experimental outcomes related to the fundamental constituents of matter. However, there are still many unanswered questions. Supersymmetry (SUSY) is an extension of the SM that aims to fill these gaps by predicting a super partner particle for each particle in the SM. This analysis has been performed earlier using Run 1 and 36 fb−1of Run 2 data. This time a dedicated search is performed using the full LHC Run 2 data of 139 fb−1at ps = 13TeV to look for the pair production of 3rd generation squarks decaying asymmetrically into a tb+Emiss/T signature resulting in 1 lepton, 2 b-jets and Emiss/T final state. The analysis was divided into bulk and compressed signal regions based on the mass difference between the top quark and ˜Χ0/1. The author’s work had been focused on the developing and validating the entire signal grid and defining and analysing the bulk region. In this signal region, this search has placed expected exclusion limits on m˜t/˜b upto 980 GeVfor m˜Χ0/1 = 110 GeV assuming Δm(˜Χ0/1, ˜Χ±/1 ) =1 GeV. This search increases the limit by ~ 150 GeV and 60 GeV when compared to the one lepton region and the combined bb+Emiss/T and tb+Emiss/T observed exclusion contours of the previous version of the analysis

Spare Block Cache Architecture to Enable Low-Voltage Operation

Power consumption is a major concern for modern processors. Voltage scaling is one of the most effective mechanisms to reduce power consumption. However, voltage scaling is limited by large memory structures, such as caches, where many cells can fail at low voltage operation. As a result, voltage scaling is limited by a minimum voltage (Vccmin), below which the processor may not operate reliably. Researchers have proposed architectural mechanisms, error detection and correction techniques, and circuit solutions to allow the cache to operate reliably at low voltages. Architectural solutions reduce cache capacity at low voltages at the expense of logic complexity. Circuit solutions change the SRAM cell organization and have the disadvantage of reducing the cache capacity (for the same area) even when the system runs at a high voltage. Error detection and correction mechanisms use Error Correction Codes (ECC) codes to keep the cache operation reliable at low voltage, but have the disadvantage of increasing cache access time. In this thesis, we propose a novel architectural technique that uses spare cache blocks to back up a set-associative cache at low voltage. In our mechanism, we perform memory tests at low voltage to detect errors in all cache lines and tag them as faulty or fault-free. We have designed shifter and adder circuits for our architecture, and evaluated our design using the SimpleScalar simulator. We constructed a fault model for our design to find the cache set failure probability at low voltage. Our evaluation shows that, at 485mV, our designed cache operates with an equivalent bit failure probability to a conventional cache operating at 782mV. We have compared instructions per cycle (IPC), miss rates, and cache accesses of our design with a conventional cache operating at nominal voltage. We have also compared our cache performance with a cache using the previously proposed Bit-Fix mechanism. Our result show that our designed spare cache mechanism is 15% more area efficient compared to Bit-Fix. Our proposed approach provides a significant improvement in power and EPI (energy per instruction) over a conventional cache and Bit-Fix, at the expense of having lower performance at high voltage

Search For A Heavy Gauge Boson W' In The Final State With An Electron And Large Missing Transverse Energy In Pp Collisions At Sqrt(S) = 7 Tev

A search for a heavy gauge boson W has been conducted by the CMS experiment at the LHC in the decay channel with an electron and large transverse / energy imbalance, E T , using proton-proton collision data corresponding to an integrated luminosity of 36 pb[-]1 . No excess above standard model expectations / is seen in the transverse mass distribution of the electron-E T system. Assuming standard-model-like couplings and decay branching fractions, a W boson with a mass less than 1.32 TeV/c2 is excluded at the 95% confidence level

High-speed optical data transmission for detector instrumentation in particle physics

This work discusses the advantage of optical transmission utilizing wavelength-division multiplexing for the read-out of experimental data in detector instrumentation in high-energy physics, astroparticle physics or photon science. A multi-channel optical transmitter is developed as the core component on a silicon-on-insulator platform. It implements Mach-Zehnder modulators with a depletion-type pn-phase shifter in each arm, while the (de )multiplexers rely on planar concave gratings. The modulator design is expected to support a symbol rate in the range 40 GBd even with a phase shifter length of 3 mm. The development of an efficient simulation method is presented, which allows for the reliable prediction of the steady-state modulator characteristics. Furthermore, this work addresses the packaging technology for grating-coupled silicon photonic components. In particular, a fabrication and assembly process for a planar fiber-to-chip coupling using angle-polished single-mode fibers is developed. A long-term-stable coupling with a small footprint is achieved, of which the coupling efficiency is only weakly dependent on ambient conditions