Parametric Test Development for RF Circuits Targeting Physical Fault Locations and Using Specification-Based Fault Definitions

The test cost of RF systems is an increasing percentage of the overall system cost. This trend is mainly due to the traditional RF testing schemes based on the full measurement of specifications over a wide range of input conditions. In this paper, we present a test development methodology for RF circuits based on a novel parametric fault defition. We target deviations in physical circuit parameters, such as a resistance or the width of a transistor. However, we consider a circuit faulty only if it violates a specification. Our test development method aims at reducing not only the number of measurements, but also the overall test hardware cost by incorporating the relative set-up cost of each measurement into our selection criteria. Experimental results on a low-noise amplifier (LNA) circuit show that our test development technique reduces the overall test time (49 %- 67%) as well as the number of required measurement set-ups (17 %- 33%) considerably. By defining the target faults based on specification violations, our technique also provides high confidence in the test quality. 1