Architectural exploration of heterogeneous memory systems

Heterogeneous systems appear as a viable design alternative for the dark silicon era. In this paradigm, a processor chip includes several different technological alternatives for implementing a certain logical block (e.g., core, on-chip memories) which cannot be used at the same time due to power constraints. The programmer and compiler are then responsible for selecting which of the alternatives should be used for maximizing performance and/or energy efficiency for a given application. This paper presents an initial approach for the exploration of different technological alternatives for the implementation of on-chip memories. It hinges on a linear programming-based model for theoretically comparing the performance offered by the available alternatives, namely SRAM and STT-RAM scratchpads or caches. Experimental results using a cycle-accurate simulation tool confirm that this is a viable model for implementation into production compilers

Author manuscript, published in "A4MMC 2010- 1st Workshop on Applications for Multi and Many Core Processors (2010)" Parallelization Strategy for CELL TV

Abstract. Consumer electronics devices are moving forward to utilize multi-core processors. We have developed a series of unique applications for TV based on Cell Broadband Engine TM (Cell/B.E.) 1. This paper introduces such applications realized by the capability of the multi-core processor, and shares the strategy we took to exploit its potential