Parallel RRT* architecture design for motion planning

A motion planning algorithm aims to calculate one obstacle-free trajectory which meets the dynamical constraints of a vehicle and leads the vehicle from the start state to the target state. RRT* (RRT star) is one sampling-based algorithm which is widely used in many applications because of its speed in quickly finding a trajectory. In contrast with basic RRT (Rapidly-exploring Random Trees) algorithm, RRT* improves trajectory optimality significantly by introducing the refinement step after setting up each tree node. This paper describes a new parallel version of the RRT* algorithm and its corresponding architecture on an FPGA (Field Programmable Gate Arrays). The refinement step is extracted and runs as a parallel process alongside a continuous tree-extending process. In order to avoid traversing all nodes in every iteration, tree nodes are stored in separate memory blocks and each block is assigned its own tree extending and refining pipelines to enhance the memory throughput. In the experimental evaluation, we take a 3-dimensional state spaces and implement the proposed architecture. The hardware implementation gives a 90 times speed improvement compared with an embedded software implementation, and a 30 times speedup compared to a desktop software implementation