Network-on-Chip

Addresses the Challenges Associated with System-on-Chip Integration Network-on-Chip: The Next Generation of System-on-Chip Integration examines the current issues restricting chip-on-chip communication efficiency, and explores Network-on-chip (NoC), a promising alternative that equips designers with the capability to produce a scalable, reusable, and high-performance communication backbone by allowing for the integration of a large number of cores on a single system-on-chip (SoC). This book provides a basic overview of topics associated with NoC-based design: communication infrastructure design, communication methodology, evaluation framework, and mapping of applications onto NoC. It details the design and evaluation of different proposed NoC structures, low-power techniques, signal integrity and reliability issues, application mapping, testing, and future trends. Utilizing examples of chips that have been implemented in industry and academia, this text presents the full architectural design of components verified through implementation in industrial CAD tools. It describes NoC research and developments, incorporates theoretical proofs strengthening the analysis procedures, and includes algorithms used in NoC design and synthesis. In addition, it considers other upcoming NoC issues, such as low-power NoC design, signal integrity issues, NoC testing, reconfiguration, synthesis, and 3-D NoC design. This text comprises 12 chapters and covers: The evolution of NoC from SoC—its research and developmental challenges NoC protocols, elaborating flow control, available network topologies, routing mechanisms, fault tolerance, quality-of-service support, and the design of network interfaces The router design strategies followed in NoCs The evaluation mechanism of NoC architectures The application mapping strategies followed in NoCs Low-power design techniques specifically followed in NoCs The signal integrity and reliability issues of NoC The details of NoC testing strategies reported so far The problem of synthesizing application-specific NoCs Reconfigurable NoC design issues Direction of future research and development in the field of NoC Network-on-Chip: The Next Generation of System-on-Chip Integration covers the basic topics, technology, and future trends relevant to NoC-based design, and can be used by engineers, students, and researchers and other industry professionals interested in computer architecture, embedded systems, and parallel/distributed systems

From FPGA to ASIC: A RISC-V processor experience

This work document a correct design flow using these tools in the Lagarto RISC- V Processor and the RTL design considerations that must be taken into account, to move from a design for FPGA to design for ASIC

Analysis and design of low-power data converters

In a large number of applications the signal processing is done exploiting both analog and digital signal processing techniques. In the past digital and analog circuits were made on separate chip in order to limit the interference and other side effects, but the actual trend is to realize the whole elaboration chain on a single System on Chip (SoC). This choice is driven by different reasons such as the reduction of power consumption, less silicon area occupation on the chip and also reliability and repeatability. Commonly a large area in a SoC is occupied by digital circuits, then, usually a CMOS short-channel technological processes optimized to realize digital circuits is chosen to maximize the performance of the Digital Signal Proccessor (DSP). Opposite, the short-channel technology nodes do not represent the best choice for analog circuits. But in a large number of applications, the signals which are treated have analog nature (microphone, speaker, antenna, accelerometers, biopotential, etc.), then the input and output interfaces of the processing chip are analog/mixed-signal conversion circuits. Therefore in a single integrated circuit (IC) both digital and analog circuits can be found. This gives advantages in term of total size, cost and power consumption of the SoC. The specific characteristics of CMOS short-channel processes such as: • Low breakdown voltage (BV) gives a power supply limit (about 1.2 V). • High threshold voltage VTH (compared with the available voltage supply) fixed in order to limit the leakage power consumption in digital applications (of the order of 0.35 / 0.4V), puts a limit on the voltage dynamic, and creates many problems with the stacked topologies. • Threshold voltage dependent on the channel length VTH = f(L) (short channel effects). • Low value of the output resistance of the MOS (r0) and gm limited by speed saturation, both causes contribute to achieving a low intrinsic gain gmr0 = 20 to 26dB. • Mismatch which brings offset effects on analog circuits. make the design of high performance analog circuits very difficult. Realizing lowpower circuits is fundamental in different contexts, and for different reasons: lowering the power dissipation gives the capability to reduce the batteries size in mobile devices (laptops, smartphones, cameras, measuring instruments, etc.), increase the life of remote sensing devices, satellites, space probes, also allows the reduction of the size and weight of the heat sink. The reduction of power dissipation allows the realization of implantable biomedical devices that do not damage biological tissue. For this reason, the analysis and design of low power and high precision analog circuits is important in order to obtain high performance in technological processes that are not optimized for such applications. Different ways can be taken to reduce the effect of the problems related to the technology: • Circuital level: a circuit-level intervention is possible to solve a specific problem of the circuit (i.e. Techniques for bandwidth expansion, increase the gain, power reduction, etc.). • Digital calibration: it is the highest level to intervene, and generally going to correct the non-ideal structure through a digital processing, these aims are based on models of specific errors of the structure. • Definition of new paradigms. This work has focused the attention on a very useful mixed-signal circuit: the pipeline ADC. The pipeline ADCs are widely used for their energy efficiency in high-precision applications where a resolution of about 10-16 bits and sampling rates above hundreds of Mega-samples per second (telecommunication, radar, etc.) are needed. An introduction on the theory of pipeline ADC, its state of the art and the principal non-idealities that affect the energy efficiency and the accuracy of this kind of data converters are reported in Chapter 1. Special consideration is put on low-voltage low-power ADCs. In particular, for ADCs implemented in deep submicron technology nodes side effects called short channel effects exist opposed to older technology nodes where undesired effects are not present. An overview of the short channel effects and their consequences on design, and also power consuption reduction techniques, with particular emphasis on the specific techniques adopted in pipelined ADC are reported in Chapter 2. Moreover, another way may be undertaken to increase the accuracy and the efficiency of an ADC, this way is the digital calibration. In Chapter 3 an overview on digital calibration techniques, and furthermore a new calibration technique based on Volterra kernels are reported. In some specific applications, such as software defined radios or micropower sensor, some circuits should be reconfigurable to be suitable for different radio standard or process signals with different charateristics. One of this building blocks is the ADC that should be able to reconfigure the resolution and conversion frequency. A reconfigurable voltage-scalable ADC pipeline capable to adapt its voltage supply starting from the required conversion frequency was developed, and the results are reported in Chapter 4. In Chapter 5, a pipeline ADC based on a novel paradigm for the feedback loop and its theory is described

Urban and extra-urban hybrid vehicles: a technological review

Pollution derived from transportation systems is a worldwide, timelier issue than ever. The abatement actions of harmful substances in the air are on the agenda and they are necessary today to safeguard our welfare and that of the planet. Environmental pollution in large cities is approximately 20% due to the transportation system. In addition, private traffic contributes greatly to city pollution. Further, “vehicle operating life” is most often exceeded and vehicle emissions do not comply with European antipollution standards. It becomes mandatory to find a solution that respects the environment and, realize an appropriate transportation service to the customers. New technologies related to hybrid –electric engines are making great strides in reducing emissions, and the funds allocated by public authorities should be addressed. In addition, the use (implementation) of new technologies is also convenient from an economic point of view. In fact, by implementing the use of hybrid vehicles, fuel consumption can be reduced. The different hybrid configurations presented refer to such a series architecture, developed by the researchers and Research and Development groups. Regarding energy flows, different strategy logic or vehicle management units have been illustrated. Various configurations and vehicles were studied by simulating different driving cycles, both European approval and homologation and customer ones (typically municipal and university). The simulations have provided guidance on the optimal proposed configuration and information on the component to be used

On orbit validation of solar sailing control laws with thin-film spacecraft

Many innovative approaches to solar sail mission and trajectory design have been proposed over the years, but very few ever have the opportunity to be validated on orbit with real spacecraft. Thin- Film Spacecraft/Lander/Rovers (TF-SL Rs) are a new class of very low cost, low mass space vehicle which are ideal for inexpensively and quickly testing in flight new approaches to solar sailing. This paper describes using TF- SLR based micro solar sails to implement a generic solar sail test bed on orbit. TF -SLRs are high area- to-mass ratio (A/m) spacecraft developed for very low cost consumer and scientific deep space missions. Typically based on a 5 μm or thinner metalised substrate, they include an integrated avionics and payload system -on-chip (SoC) die bonded to the substrate with passive components and solar cells printed or deposited by Metal Organic Chemical Vapour Deposition (MOCVD). The avionics include UHF/S- band transceivers, processors, storage, sensors and attitude control provided by integrated magnetorquers and reflectivity control devices. Resulting spacecraft have a typical thickness of less than 50 μm, are 80 mm in diameter, and have a mass of less than 100 mg resulting in sail loads of less than 20 g/m 2 . TF -SLRs are currently designed for direct dispensing in swarms from free flying 0.5U Interplanetary CubeSats or dispensers attached to launch vehicles. Larger 160 mm, 320 mm and 640 mm diameter TF -SLRs utilizing a CubeSat compatible TWIST deployment mechanism that maintains the high A/m ratio are also under development. We are developing a mission to demonstrate the utility of these devices as a test bed for experimenting with a variety of mission designs and control laws. Batches of up to one hundred TF- SLRs will be released on earth escape trajectories, with each batch executing a heterogeneous or homogenous mixture of control laws and experiments. Up to four releases at different points in orbit are currently envisaged with experiments currently being studied in MATLAB and GMA T including managing the rate of separation of individual spacecraft, station keeping and single deployment/substantially divergent trajectory development. It is also hoped to be able to demonstrate uploading new experiment designs while in orbit and to make this capability available to researchers around the world. A suitable earth escape mission is currently being sought and it is hoped the test bed could be on orbit in 2017/18

Hardware acceleration architectures for MPEG-Based mobile video platforms: a brief overview

This paper presents a brief overview of past and current hardware acceleration (HwA) approaches that have been proposed for the most computationally intensive compression tools of the MPEG-4 standard. These approaches are classified based on their historical evolution and architectural approach. An analysis of both evolutionary and functional classifications is carried out in order to speculate on the possible trends of the HwA architectures to be employed in mobile video platforms

Economic optimization of component sizing for residential battery storage systems

Battery energy storage systems (BESS) coupled with rooftop-mounted residential photovoltaic (PV) generation, designated as PV-BESS, draw increasing attention and market penetration as more and more such systems become available. The manifold BESS deployed to date rely on a variety of different battery technologies, show a great variation of battery size, and power electronics dimensioning. However, given today's high investment costs of BESS, a well-matched design and adequate sizing of the storage systems are prerequisites to allow profitability for the end-user. The economic viability of a PV-BESS depends also on the battery operation, storage technology, and aging of the system. In this paper, a general method for comprehensive PV-BESS techno-economic analysis and optimization is presented and applied to the state-of-art PV-BESS to determine its optimal parameters. Using a linear optimization method, a cost-optimal sizing of the battery and power electronics is derived based on solar energy availability and local demand. At the same time, the power flow optimization reveals the best storage operation patterns considering a trade-off between energy purchase, feed-in remuneration, and battery aging. Using up to date technology-specific aging information and the investment cost of battery and inverter systems, three mature battery chemistries are compared; a lead-acid (PbA) system and two lithium-ion systems, one with lithium-iron-phosphate (LFP) and another with lithium-nickel-manganese-cobalt (NMC) cathode. The results show that different storage technology and component sizing provide the best economic performances, depending on the scenario of load demand and PV generation.Web of Science107art. no. 83

Mixed-integer-linear-programming-based energy management system for hybrid PV-wind-battery microgrids: Modeling, design, and experimental verification

© 2017 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other worksMicrogrids are energy systems that aggregate distributed energy resources, loads, and power electronics devices in a stable and balanced way. They rely on energy management systems to schedule optimally the distributed energy resources. Conventionally, many scheduling problems have been solved by using complex algorithms that, even so, do not consider the operation of the distributed energy resources. This paper presents the modeling and design of a modular energy management system and its integration to a grid-connected battery-based microgrid. The scheduling model is a power generation-side strategy, defined as a general mixed-integer linear programming by taking into account two stages for proper charging of the storage units. This model is considered as a deterministic problem that aims to minimize operating costs and promote self-consumption based on 24-hour ahead forecast data. The operation of the microgrid is complemented with a supervisory control stage that compensates any mismatch between the offline scheduling process and the real time microgrid operation. The proposal has been tested experimentally in a hybrid microgrid at the Microgrid Research Laboratory, Aalborg University.Peer ReviewedPostprint (author's final draft