Efficient and Linear CMOS Power Amplifier and Front-end Design for Broadband Fully-Integrated 28-GHz 5G Phased Arrays

Demand for data traffic on mobile networks is growing exponentially with time and on a global scale. The emerging fifth-generation (5G) wireless standard is being developed with millimeter-wave (mm-Wave) links as a key technological enabler to address this growth by a 2020 time frame. The wireless industry is currently racing to deploy mm-Wave mobile services, especially in the 28-GHz band. Previous widely-held perceptions of fundamental propagation limitations were overcome using phased arrays. Equally important for success of 5G is the development of low-power, broadband user equipment (UE) radios in commercial-grade technologies. This dissertation demonstrates design methodologies and circuit techniques to tackle the critical challenge of key phased array front-end circuits in low-cost complementary metal oxide semiconductor (CMOS) technology. Two power amplifier (PA) proof-of-concept prototypes are implemented in deeply scaled 28- nm and 40-nm CMOS processes, demonstrating state-of-the-art linearity and efficiency for extremely broadband communication signals. Subsequently, the 40 nm PA design is successfully embedded into a low-power fully-integrated transmit-receive front-end module. The 28 nm PA prototype in this dissertation is the first reported linear, bulk CMOS PA targeting low-power 5G mobile UE integrated phased array transceivers. An optimization methodology is presented to maximizing power added efficiency (PAE) in the PA output stage at a desired error vector magnitude (EVM) and range to address challenging 5G uplink requirements. Then, a source degeneration inductor in the optimized output stage is shown to further enable its embedding into a two-stage transformer-coupled PA. The inductor helps by broadening inter-stage impedance matching bandwidth, and helping to reduce distortion. Designed and fabricated in 1P7M 28 nm bulk CMOS and using a 1 V supply, the PA achieves +4.2 dBm/9% measured Pout/PAE at −25 dBc EVM for a 250 MHz-wide, 64-QAM orthogonal frequency division multiplexing (OFDM) signal with 9.6 dB peak-to-average power ratio (PAPR). The PA also achieves 35.5%/10% PAE for continuous wave signals at saturation/9.6dB back-off from saturation. To the best of the author’s knowledge, these are the highest measured PAE values among published K- and K a-band CMOS PAs to date. To drastically extend the communication bandwidth in 28 GHz-band UE devices, and to explore the potential of CMOS technology for more demanding access point (AP) devices, the second PA is demonstrated in a 40 nm process. This design supports a signal radio frequency bandwidth (RFBW) >3× the state-of-the-art without degrading output power (i.e. range), PAE (i.e. battery life), or EVM (i.e. amplifier fidelity). The three-stage PA uses higher-order, dual-resonance transformer matching networks with bandwidths optimized for wideband linearity. Digital gain control of 9 dB range is integrated for phased array operation. The gain control is a needed functionality, but it is largely absent from reported high-performance mm-Wave PAs in the literature. The PA is fabricated in a 1P6M 40 nm CMOS LP technology with 1.1 V supply, and achieves Pout/PAE of +6.7 dBm/11% for an 8×100 MHz carrier aggregation 64-QAM OFDM signal with 9.7 dB PAPR. This PA therefore is the first to demonstrate the viability of CMOS technology to address even the very challenging 5G AP/downlink signal bandwidth requirement. Finally, leveraging the developed PA design methodologies and circuits, a low power transmit-receive phased array front-end module is fully integrated in 40 nm technology. In transmit-mode, the front-end maintains the excellent performance of the 40 nm PA: achieving +5.5 dBm/9% for the same 8×100 MHz carrier aggregation signal above. In receive-mode, a 5.5 dB noise figure (NF) and a minimum third-order input intercept point (IIP₃) of −13 dBm are achieved. The performance of the implemented CMOS frontend is comparable to state-of-the-art publications and commercial products that were very recently developed in silicon germanium (SiGe) technologies for 5G communication

A survey on RF and microwave doherty power amplifier for mobile handset applications

This survey addresses the cutting-edge load modulation microwave and radio frequency power amplifiers for next-generation wireless communication standards. The basic operational principle of the Doherty amplifier and its defective behavior that has been originated by transistor characteristics will be presented. Moreover, advance design architectures for enhancing the Doherty power amplifier’s performance in terms of higher efficiency and wider bandwidth characteristics, as well as the compact design techniques of Doherty amplifier that meets the requirements of legacy 5G handset applications, will be discussed.Agencia Estatal de Investigación | Ref. TEC2017-88242-C3-2-RFundação para a Ciência e a Tecnologia | Ref. UIDP/50008/201

Optimization Of 5.7 Ghz Class E Power Amplifier For The Application Of Envelope Elimination And Restoration

Tez (Yüksek Lisans) -- İstanbul Teknik Üniversitesi, Fen Bilimleri Enstitüsü, 2007Thesis (M.Sc.) -- İstanbul Technical University, Institute of Science and Technology, 2007Rekabetin yoğun olduğu günümüzde tasarımcılar hafif, boyutları daha küçük ve düşük güçle çalışan yüksek performanslı ürün geliştirmenin yollarını aramaktadırlar. RF alıcı uygulamalarında güç kuvvetlendiricileri en fazla güç sarfiyatının olduğu bölümdür. Kablosuz iletişim sistemlerinde güç küvvetlendiricisi verimi maliyeti direkt olarak etkilemektedir. Teorik olarak %100 verim elde edilebilen E-sınıfı güç kuvvetlendiricileri transistorların açık/kapalı durum geçişlerinde güç sarfiyatını minimize edebilmektedir. Ayrıca çıkış gerilimi kaynak gerilimi ile doğrusal değişmektedir. Bu çalışmada E sınıfı güç kuvvetlendiricilerinin tasarım metodları ele alınmıştır. 5.7 GHz de çalışan birinde toplu devre elemanları, diğerinde transmisyon hattı elemanları kullanımış E sınıfı güç kuvvetlendiricileri tasarlanmıştır. Her iki devrede de %50 güç ekli verim (GEV) ve 500mW çıkış gücü elde edilmiştir. Sinyaldeki bozulmayı azaltmak için başvurulan doğrusallaştırma yöntemi Zarf Yoketme ve Tekrar Oluşturma metodudur. E sınıfı kuvvetlendiricinin Zarf Yoketme ve Tekrar Oluşturma yöntemi kullanılarak doğrusallaştırılmasıyla IMD bileşenlerinde 7.5 dB azalmış olup seviyesi gerçek işaretin 20dB altındadır.In today’s competitive, manufactures and product developers are seeking ways to build high performance devices that are lighter in weight, smaller in size and operating at lower power. In transceiver applications one module is responsible for a large portion of the power consumption - the power amplifier. The efficiency of the power amplifier has a direct impact on the cost of the wireless communication system. The class-E amplifier has a maximum theoretical efficiency of 100%. Class E power amplifiers have the ability to minimize power loss during on/off transitions of the transistor. Also, the output voltage varies linearly with the supply voltage. This thesis describes the design and the linearization methodology of the Class E amplifiers. Two class-E amplifiers operating at 5.7 GHz are presented. One of them is a lumped elements based circuit and the other is a transmission lines based circuit. Both circuit show good performance with 50% PAE and have 500mW output power. Envelope elimination and restoration is the linearization method chosen to achieve reduction of signal distortion. Linearization Class E PA using EER system provides an additional 7.5 dB reduction in intermodulation distortion products, achieving a minimum distortion level of 20 dB below the fundamental signals.Yüksek LisansM.Sc

The Switched Mode Power Amplifiers

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Advanced High Efficiency Architectures for Next Generation Wireless Communications

L'abstract è presente nell'allegato / the abstract is in the attachmen