2 research outputs found
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The analysis and synthesis of a parallel sorting engine
This thesis is concerned with the development of a unique
parallel sort-merge system suitable for implementation in VLSI.
Two new sorting subsystems, a high performance VLSI sorter and a
four-way merger, were also realized during the development
process. In addition, the analysis of several existing parallel sorting
architectures and algorithms was carried out.
Algorithmic time complexity, VLSI processor performance, and
chip area requirements for the existing sorting systems were
evaluated. The rebound sorting algorithm was determined to be the
most efficient among those considered. The rebound sorter
algorithm was implemented in hardware as a systolic array with
external expansion capability.
The second phase of the research involved analyzing several
parallel merge algorithms and their buffer management schemes.
The dominant considerations for this phase of the research were the
achievement of minimum VLSI chip area, design complexity, and logic delay. It was determined that the proposed merger
architecture could be implemented in several ways. Selecting the
appropriate microarchitecture for the merger, given the constraints
of chip area and performance, was the major problem. The tradeoffs
associated with this process are outlined.
Finally, a pipelined sort-merge system was implemented in
VLSI by combining a rebound sorter and a four-way merger on a
single chip. The final chip size was 416 mils by 432 mils. Two
micron CMOS technology was utilized in this chip realization. An
overall throughput rate of 10M bytes/sec was achieved. The
prototype system developed is capable of sorting thirty two 2-byte
keys during each merge phase. If extended, this system is capable of
economically sorting files of 100M bytes or more in size. In order to
sort larger files, this design should be incorporated in a disk-based
sort-merge system. A simplified disk I/O access model for such a
system was studied. In this study the sort-merge system was
assumed to be part of a disk controller subsystem