Optimal Alphabetic Ternary Trees

We give a new algorithm to construct optimal alphabetic ternary trees, where every internal node has at most three children. This algorithm generalizes the classic Hu-Tucker algorithm, though the overall computational complexity has yet to be determined

Flexible Memory Protection with Dynamic Authentication Trees

As computing appliances increase in use and handle more critical information and functionalities, the importance of security grows even greater. In cases where the device processes sensitive data or performs important functionality, an attacker may be able to read or manipulate it by accessing the data bus between the processor and memory itself. As it is impossible to provide physical protection to the piece of hardware in use, it is important to provide protection against revealing confidential information and securing the device\u27s intended operation. Defense against bus attacks such as spoofing, splicing, and replay attacks are of particular concern. Traditional memory authentication techniques, such as hashes and message authentication codes, are costly when protecting off-chip memory during run-time. Balanced authentication trees such as the well-known Merkle tree or TEC-Tree are widely used to reduce this cost. While authentication trees are less costly than conventional techniques it still remains expensive. This work proposes a new method of dynamically updating an authentication tree structure based on a processor\u27s memory access pattern. Memory addresses that are more frequently accessed are dynamically shifted to a higher tree level to reduce the number of memory accesses required to authenticate that address. The block-level AREA technique is applied to allow for data confidentiality with no additional cost. An HDL design for use in an FPGA is provided as a transparent and highly customizable AXI-4 memory controller. The memory controller allows for data confidentiality and authentication for random-access memory with different speed or memory size constraints. The design was implemented on a Zynq 7000 system-on-chip using the processor to communicate with the hardware design. The performance of the dynamic tree design is comparable to the TEC-Tree in several memory access patterns. The TEC-Tree performs better than a dynamic design in particular applications; however, speedup over the TEC-Tree is possible to achieve when applied in scenarios that frequently accessed previously processed data

Optimum alphabetic binary trees

We describe a modification of the Hu-Tucker algorithm for constructing an optimal alphabetic tree that runs in O(n) time for several classes of inputs. These classes can be described in simple terms and can be detected in linear time. We also give simple conditions and a linear algorithm for determining if two adjacent nodes will be combined in the optimal alphabetic tree. (orig.)SIGLEAvailable from TIB Hannover: RN 4052(95850) / FIZ - Fachinformationszzentrum Karlsruhe / TIB - Technische InformationsbibliothekDEGerman

Optimum Alphabetic Binary Trees

We describe a modification of the Hu--Tucker algorithm for constructing an optimal alphabetic tree that runs in O(n) time for several classes of inputs. These classes can be described in simple terms and can be detected in linear time. We also give simple conditions and a linear algorithm for determining, in some cases, if two adjacent nodes will be combined in the optimal alphabetic tree