OPTIMIZATION OF THE PARALLEL TECHNIQUE FOR COMPILED UNIT-DELAY SIMULATION

The parallel technique of compiled simulation is a purely compiled method for unitdelay simulation that is based on the concepts of levelized compiled simulation and parallel fault simulation. Although the parallel technique provides very rapid simulations with a reasonable amount of generated code, there are several opportunities for optimizing the generated code. This paper presents two optimization schemes which are called bit-field trimming and shift-elimination. Two different methods of shift elimination are presented. Performance results are presented for all optimization techniques. These results show that using both optimizations schemes together provides for an average performanc