69,670 research outputs found
Linear decomposition of approximate multi-controlled single qubit gates
We provide a method for compiling approximate multi-controlled single qubit
gates into quantum circuits without ancilla qubits. The total number of
elementary gates to decompose an n-qubit multi-controlled gate is proportional
to 32n, and the previous best approximate approach without auxiliary qubits
requires 32nk elementary operations, where k is a function that depends on the
error threshold. The proposed decomposition depends on an optimization
technique that minimizes the CNOT gate count for multi-target and
multi-controlled CNOT and SU(2) gates. Computational experiments show the
reduction in the number of CNOT gates to apply multi-controlled U(2) gates. As
multi-controlled single-qubit gates serve as fundamental components of quantum
algorithms, the proposed decomposition offers a comprehensive solution that can
significantly decrease the count of elementary operations employed in quantum
computing applications
Arithmetic Operations in Multi-Valued Logic
This paper presents arithmetic operations like addition, subtraction and
multiplications in Modulo-4 arithmetic, and also addition, multiplication in
Galois field, using multi-valued logic (MVL). Quaternary to binary and binary
to quaternary converters are designed using down literal circuits. Negation in
modular arithmetic is designed with only one gate. Logic design of each
operation is achieved by reducing the terms using Karnaugh diagrams, keeping
minimum number of gates and depth of net in to consideration. Quaternary
multiplier circuit is proposed to achieve required optimization. Simulation
result of each operation is shown separately using Hspice.Comment: 12 Pages, VLSICS Journal 201
Neuro-Fuzzy Computing System with the Capacity of Implementation on Memristor-Crossbar and Optimization-Free Hardware Training
In this paper, first we present a new explanation for the relation between
logical circuits and artificial neural networks, logical circuits and fuzzy
logic, and artificial neural networks and fuzzy inference systems. Then, based
on these results, we propose a new neuro-fuzzy computing system which can
effectively be implemented on the memristor-crossbar structure. One important
feature of the proposed system is that its hardware can directly be trained
using the Hebbian learning rule and without the need to any optimization. The
system also has a very good capability to deal with huge number of input-out
training data without facing problems like overtraining.Comment: 16 pages, 11 images, submitted to IEEE Trans. on Fuzzy system
qTorch: The Quantum Tensor Contraction Handler
Classical simulation of quantum computation is necessary for studying the
numerical behavior of quantum algorithms, as there does not yet exist a large
viable quantum computer on which to perform numerical tests. Tensor network
(TN) contraction is an algorithmic method that can efficiently simulate some
quantum circuits, often greatly reducing the computational cost over methods
that simulate the full Hilbert space. In this study we implement a tensor
network contraction program for simulating quantum circuits using multi-core
compute nodes. We show simulation results for the Max-Cut problem on 3- through
7-regular graphs using the quantum approximate optimization algorithm (QAOA),
successfully simulating up to 100 qubits. We test two different methods for
generating the ordering of tensor index contractions: one is based on the tree
decomposition of the line graph, while the other generates ordering using a
straight-forward stochastic scheme. Through studying instances of QAOA
circuits, we show the expected result that as the treewidth of the quantum
circuit's line graph decreases, TN contraction becomes significantly more
efficient than simulating the whole Hilbert space. The results in this work
suggest that tensor contraction methods are superior only when simulating
Max-Cut/QAOA with graphs of regularities approximately five and below. Insight
into this point of equal computational cost helps one determine which
simulation method will be more efficient for a given quantum circuit. The
stochastic contraction method outperforms the line graph based method only when
the time to calculate a reasonable tree decomposition is prohibitively
expensive. Finally, we release our software package, qTorch (Quantum TensOR
Contraction Handler), intended for general quantum circuit simulation.Comment: 21 pages, 8 figure
A high-Tc 4-bit periodic threshold analog-to-digital converter
Using ramp-type Josephson junctions a 4-bit periodic threshold ADC has been designed, fabricated and tested. Practical design constraints will be discussed in terms of noise immunity, flux flow, available technology, switching speed etc. In a period of four years we fabricated about 100 chips in order to bring the technology to an acceptable level and to test various designs and circuit layouts. This resulted in a basic comparator that is rather insensitive to the stray field generated by the analog input signal or variations in mask alignment during fabrication. The input signal is fed into the comparators using a resistive divider network. Full functionality at low frequencies has been demonstrate
A Multi-objective Perspective for Operator Scheduling using Fine-grained DVS Architecture
The stringent power budget of fine grained power managed digital integrated
circuits have driven chip designers to optimize power at the cost of area and
delay, which were the traditional cost criteria for circuit optimization. The
emerging scenario motivates us to revisit the classical operator scheduling
problem under the availability of DVFS enabled functional units that can
trade-off cycles with power. We study the design space defined due to this
trade-off and present a branch-and-bound(B/B) algorithm to explore this state
space and report the pareto-optimal front with respect to area and power. The
scheduling also aims at maximum resource sharing and is able to attain
sufficient area and power gains for complex benchmarks when timing constraints
are relaxed by sufficient amount. Experimental results show that the algorithm
that operates without any user constraint(area/power) is able to solve the
problem for most available benchmarks, and the use of power budget or area
budget constraints leads to significant performance gain.Comment: 18 pages, 6 figures, International journal of VLSI design &
Communication Systems (VLSICS
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