AlN/GaN MOS-HEMTs technology

The ever increasing demand for higher power devices at higher frequencies has prompted much research recently into the aluminium nitride/gallium nitride high electron mobility transistors (AlN/GaN HEMTs) in response to theoretical predictions of higher performance devices. Despite having superior material properties such as higher two-dimensional electron gas (2DEG) densities and larger breakdown field as compared to the conventional aluminium gallium nitride (AlGaN)/GaN HEMTs, the AlN/GaN devices suffer from surface sensitivity, high leakage currents and high Ohmic contact resistances. Having very thin AlN barrier layer of ∼ 3 nm makes the epilayers very sensitive to liquids coming in contact with the surface. Exposure to any chemical solutions during device processing degrades the surface properties, resulting in poor device performance. To overcome the problems, a protective layer is employed during fabrication of AlN/GaN-based devices. However, in the presence of the protective/passivation layers, formation of low Ohmic resistance source and drain contact becomes even more difficult. In this work, thermally grown aluminium oxide (Al2O3) was used as a gate di- electric and surface passivation for AlN/GaN metal-oxide-semiconductor (MOS)-HEMTs. Most importantly, the Al2O3 acts as a protection layer during device processing. The developed technique allows for a simple and effective wet etching optimisation using 16H3PO4:HNO3:2H2O solution to remove Al from the Ohmic contact regions prior to the formation of Al2O3 and Ohmic metallisation. Low Ohmic contact resistance (0.76Ω.mm) as well as low sheet resistance (318Ω/square) were obtained after optimisation. Significant reduction in the gate leakage currents was observed when employing an additional layer of thermally grown Al2O3 on the mesa sidewalls, particularly in the region where the gate metallisation overlaps with the exposed channel edge. A high peak current ∼1.5 A/mm at VGS=+3 V and a current-gain cutoff frequency, fT , and maximum oscillation frequency, fMAX , of 50 GHz and 40 GHz, respectively, were obtained for a device with 0.2 μm gate length and 100 μm gate width. The measured breakdown voltage, VBR, of a two-finger MOS-HEMT with 0.5μm gate length and 100 μm gate width was 58 V. Additionally, an approach based on an accurate estimate of all the small-signal equivalent circuit elements followed by optimisation of these to get the actual element values was also developed for AlN/GaN MOS-HEMTs. The extracted element values provide feedback for further device process optimisation. The achieved results indicate the suitability of thermally grown Al2O3 for AlN/GaN-based MOS-HEMT technology for future high frequency power applications

The development of sub-25 nm III-V High Electron Mobility Transistors

High Electron Mobility Transistors (HEMTs) are crucially important devices in microwave circuit applications. As the technology has matured, new applications have arisen, particularly at millimetre-wave and sub-millimetre wave frequencies. There now exists great demand for low-visibility, security and medical imaging in addition to telecommunications applications operating at frequencies well above 100 GHz. These new applications have driven demand for high frequency, low noise device operation; key areas in which HEMTs excel. As a consequence, there is growing incentive to explore the ultimate performance available from such devices. As with all FETs, the key to HEMT performance optimisation is the reduction of gate length, whilst optimally scaling the rest of the device and minimising parasitic extrinsic influences on device performance. Although HEMTs have been under development for many years, key performance metrics have latterly slowed in their evolution, largely due to the difficulty of fabricating devices at increasingly nanometric gate lengths and maintaining satisfactory scaling and device performance. At Glasgow, the world-leading 50 nm HEMT process developed in 2003 had not since been improved in the intervening five years. This work describes the fabrication of sub-25 nm HEMTs in a robust and repeatable manner by the use of advanced processing techniques: in particular, electron beam lithography and reactive ion etching. This thesis describes firstly the development of robust gate lithography for sub-25 nm patterning, and its incorporation into a complete device process flow. Secondly, processes and techniques for the optimisation of the complete device are described. This work has led to the successful fabrication of functional 22 nm HEMTs and the development of 10 nm scale gate pattern transfer: simultaneously some of the shortest gate length devices reported and amongst the smallest scale structures ever lithographically defined on III-V substrates. The first successful fabrication of implant-isolated planar high-indium HEMTs is also reported amongst other novel secondary processes

Current collapse and device degradation in AlGaN/GaN heterostructure field effect transistors

A spectrum of phenomena related to the reliability of AlGaN/GaN HEMTs are investigated in this thesis using numerical simulations. The focus is on trap related phenomena that lead to decrease in the power output and failure of devices, i.e. the current collapse and the device degradation. The current collapse phenomenon has been largely suppressed using SiN passivation, but there are gaps in the understanding of the process leading to this effect. Device degradation, on the other side, is a pending problem of current devices and an obstacle to wide penetration of the market. Calibration of I-V measurements of two devices is performed with high accuracy to provide a trustworthy starting point for modelling the phenomena of interest. Traditionally, in simulations of nitride based HEMTs, only direct piezoelectric effect is taken into account and the resulting interface charge is thence independent of the electric field. In this work, the impact of the electric field via the converse piezoelectric effect is taken into account and its impact on the bound charge and the drain current is studied, as a refinement of the simulation methodology. It is widely believed that the current collapse is caused by a virtual gate, i.e. electrons leaked to the surface of the device. We have found a charge distribution that reproduced the I-V measurement that shows current collapse, hence validating the concept of the virtual gate. While it was previously shown that the virtual gate has a similar impact on the I-V curve as is observed during the current collapse, we believe that this is for the first time that a wide range of gate and drain voltages was calibrated. High gate/drain voltage leading to permanent degradation was also investigated. The hypothesis that stress induced defects and dislocations might be responsible for the degradation was tested but not fully confirmed. Finally, the leakage of electrons thought to be responsible for formation of the virtual gate and the current collapse due to the Poole-Frenkel emission, is simulated in order to explain the surface charge distribution responsible for the current collapse and deduced in Chapter 5

Design and characterization of GaAs multilayer CPW components and circuits for advanced MMICs

With the demand of modern wireless communications, monolithic microwave integrated circuit (MMIC) has become a very promising technique as it is mass-productive, low loss and highly integrated. Microstrip and Coplanar Waveguide (CPW) are both widely used in MMIC. Particularly, CPW has seen a rapid increase on research works recent years due to its unique capability including having less parasitic contribution to the circuit. In this thesis, a novel 3-D multilayer CPW technique is presented. Semi-insulating (S.I.) GaAs substrate, polyimide dielectric layers and Titanium/Gold metal layers are employed in this five-layer structure. The active devices are based on GaAs pHEMTs technology provided by Filtronic Compound Semiconductor Ltd. The fabricated components are simulated and characterized by Agilent Advanced Design System (ADS) and Momentum E.M simulator. A novel Open-short-through de-embedding technique is developed and applied to the passive circuits in order to reduce the impact of pads on probing. A new library of components and circuits are built in this work. Various structures of 3-D CPW transmission lines are designed and characterized to demonstrate the low-loss and highly compact characters. Meanwhile, the influence of various combinations of metal and dielectric layers is studied in order to provide designers with great flexibility for the realization of novel compact transmission lines for 3D MMICs. The effect of temperature on the performance of the transmission lines has also been investigated. Moreover, a set of compact capacitors are designed and proven to have high capacitance density with low parasitics. Finally, based on the extraction of pHEMT parameters from circuit characterization and analysis program (IC-CAP), RF switch and active filter MMICs have been designed and simulated to provide references for further development of 3-D multilayer CPW circuits.EThOS - Electronic Theses Online ServiceGBUnited Kingdo

Innovative Approaches for AlGaN/GaN-based Technology

Gallium Nitride (GaN) has been proven to be a very suitable material for advanced power electronics on account of its outstanding material properties. Today, researchers are exploring GaN-based high electron mobility transistors (HEMTs) for conventional as well as high-end solutions in the range of 600 – 1200 V. However, thermal and power density limitations have impeded the achievement of the peak operational capability of AlGaN/GaN HEMTs. GaN-on-Diamond technology has proven to be a feasible solution to reduce thermal resistance and increase power density of AlGaN/GaN HEMTs for RF applications. The work presented in this thesis is focused on the realisation of high-voltage GaN-on-Diamond power semiconductor devices. This goal was achieved through extensive numerical simulations applied to device design, fabrication, and characterisation. The fabricated devices include conventional AlGaN/GaN HEMT design in circular and linear form with and without field plate engineering. The circular GaN-on-Diamond HEMTs with gate width of ~ 430 μm, gate length of 3 μm, gate-to-drain separation of 17 μm and source field plate length of 3 μm have shown breakdown voltage of ~ 1.1 kV. In this work a new concept of normally-off optically-controlled AlGaN/GaN-based power semiconductor device is proposed. A simulation study has been carried out in order to explore the DC characteristics, switching characteristics, breakdown voltage, and current gain of these novel devices. The typical structure comprises a 20 nm of undoped Al0.23Ga0.77N barrier layer, a 1.1 μm undoped-GaN buffer layer and a p-doped region (to locally deplete the electron channel and ensure a normally-off operation). The simulation study shows that the gain and the breakdown voltage of the device are highly dependent on the depth of the p-doped region. At a particular depth of the p-doped region of 500 nm the gain of the device is 970 (at light intensity of 7 W/cm2) and the breakdown voltage is ~ 350 V. The rise and fall times of the device is found to be 0.4 μsec and 0.3 μsec respectively. The simulation results show a significant potential of the proposed structure for high-frequency and high-power applications