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1 research outputs found
Optimisation of test architecture in three‐dimensional stacked integrated circuits for partial stack/complete stack using hard system‐on‐chips
Author
Chandan Giri
Hafizur Rahaman
+6 more
Iyengar V.
Lee H.S.
Loh H.
Noia B.
Noia B.
Surajit Kumar Roy
Publication venue
'Institution of Engineering and Technology (IET)'
Publication date
Field of study
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