Energy-aware MPC co-design for DC-DC converters

In this paper, we propose an integrated controller design methodology for the implementation of an energy-aware explicit model predictive control (MPC) algorithms, illustrat- ing the method on a DC-DC converter model. The power consumption of control algorithms is becoming increasingly important for low-power embedded systems, especially where complex digital control techniques, like MPC, are used. For DC-DC converters, digital control provides better regulation, but also higher energy consumption compared to standard analog methods. To overcome the limitation in energy efficiency, instead of addressing the problem by implementing sub-optimal MPC schemes, the closed-loop performance and the control algorithm power consumption are minimized in a joint cost function, allowing us to keep the controller power efficiency closer to an analog approach while maintaining closed-loop op- timality. A case study for an implementation in reconfigurable hardware shows how a designer can optimally trade closed-loop performance with hardware implementation performance

Lower bounds on the performance of Analog to Digital Converters

This paper deals with the task of finding certified lower bounds for the performance of Analog to Digital Converters (ADCs). A general ADC is modeled as a causal, discrete-time dynamical system with outputs taking values in a finite set. We define the performance of an ADC as the worst-case average intensity of the filtered input matching error. The input matching error is the difference between the input and output of the ADC. This error signal is filtered using a shaping filter, the passband of which determines the frequency region of interest for minimizing the error. The problem of finding a lower bound for the performance of an ADC is formulated as a dynamic game problem in which the input signal to the ADC plays against the output of the ADC. Furthermore, the performance measure must be optimized in the presence of quantized disturbances (output of the ADC) that can exceed the control variable (input of the ADC) in magnitude. We characterize the optimal solution in terms of a Bellman-type inequality. A numerical approach is presented to compute the value function in parallel with the feedback law for generating the worst case input signal. The specific structure of the problem is used to prove certain properties of the value function that allow for iterative computation of a certified solution to the Bellman inequality. The solution provides a certified lower bound on the performance of any ADC with respect to the selected performance criteria.United States. Army Research Office. Efficient Linearized All-Silicon Transmitter IC

Architectural Improvements Towards an Efficient 16-18 Bit 100-200 MSPS ADC

As Data conversion systems continue to improve in speed and resolution, increasing demands are placed on the performance of high-speed Analog to Digital Conversion systems. This work makes a survey about all these and proposes a suitable architecture in order to achieve the desired specifications of 100-200MS/s with 16-18 bit of resolution. The main architecture is based on paralleled structures in order to achieve high sampling rate and at the same time high resolution. In order to solve problems related to Time-interleaved architectures, an advanced randomization method was introduced. It combines randomization and spectral shaping of mismatches. With a simple low-pass filter the method can, compared to conventional randomization algorithms, improve the SFDR as well as the SINAD. The main advantage of this technique over previous ones is that, because the algorithm only need that ADCs are ordered basing on their time mismatches, the absolute accuracy of the mismatch identification method does not matter and, therefore, the requirements on the timing mismatch identification are very low. In addition to that, this correction system uses very simple algorithms able to correct not only for time but also for gain and offset mismatches

Frequency selective analog to digital converter design : optimality, fundamental limitations, and performance bounds

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2013.This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.Cataloged from student-submitted PDF version of thesis.Includes bibliographical references (p. 131-137).In this thesis, the problem of analysis and design of Analog to Digital Converters (ADCs) is studied within an optimal feedback control framework. A general ADC is modeled as a causal, discrete-time dynamical system with outputs taking values in a finite set. The performance measure is defined as the worst-case average intensity of the filtered input-matching error, i.e., the frequency weighted difference between the input and output of the ADC. An exact analytic solution with conditions for optimality of a class of ADCs is presented in terms of the quantizer step size and range, resulting in a class of optimal ADCs that can be viewed as generalized Delta-Sigma Modulators (DSMs). An analytic expression for the performance of generalized DSMs is given. Furthermore, separation of quantization and control for this class of ADCs is proven under some technical conditions. When the technical conditions needed for establishing separation of quantization and control and subsequently optimality of the analytical solution to ADC design problem are not satisfied, suboptimal ADC designs are characterized in terms of solutions of a Bellman-type inequality. A computational framework is presented for designing suboptimal ADCs, providing certified upper and lower bounds on the performance.by Mitra M. Osqui.Ph.D