Optimal Equivalent Circuits for Interconnect Delay Calculations Using Moments

In performance-driven interconnect design, delay estimators are used to determine both the topology and the layout of good routing trees. We address the class of moment-matching, or moment representation, methods used to simulate interconnects modeled as distributed RC or RLC lines. We provide accurate 2- and 3-segment equivalent circuits for the distributed RLC and distributed RC models. Our equivalent circuits approximate a distributed RLC structure accurately up to second degree terms. We have evaluated our models using the two-pole methodology for voltage response calculations. Previous approximate two-pole approaches have at least 14% error even for small test cases. As routing trees become bigger and interconnection lines become longer, our approach has greater advantages in both accuracy and simulation complexity. 1 Overview Accurate calculation of propagation delay in VLSI interconnects is critical to the design of high speed systems. Direct simulation codes such as SPICE ..