On the Effect of Quantum Interaction Distance on Quantum Addition Circuits

We investigate the theoretical limits of the effect of the quantum interaction distance on the speed of exact quantum addition circuits. For this study, we exploit graph embedding for quantum circuit analysis. We study a logical mapping of qubits and gates of any $\Omega(\log n)$-depth quantum adder circuit for two $n$-qubit registers onto a practical architecture, which limits interaction distance to the nearest neighbors only and supports only one- and two-qubit logical gates. Unfortunately, on the chosen $k$-dimensional practical architecture, we prove that the depth lower bound of any exact quantum addition circuits is no longer $\Omega(\log {n})$, but $\Omega(\sqrt[k]{n})$. This result, the first application of graph embedding to quantum circuits and devices, provides a new tool for compiler development, emphasizes the impact of quantum computer architecture on performance, and acts as a cautionary note when evaluating the time performance of quantum algorithms.Comment: accepted for ACM Journal on Emerging Technologies in Computing System

Expansion of layouts of complete binary trees into grids

AbstractLet Th be the complete binary tree of height h. Let M be the infinite grid graph with vertex set Z2, where two vertices (x1,y1) and (x2,y2) of M are adjacent if and only if |x1−x2|+|y1−y2|=1. Suppose that T is a tree which is a subdivision of Th and is also isomorphic to a subgraph of M. Motivated by issues in optimal VLSI design, we show that the point expansion ratio n(T)/n(Th)=n(T)/(2h+1−1) is bounded below by 1.122 for h sufficiently large. That is, we give bounds on how many vertices of degree 2 must be inserted along the edges of Th in order that the resulting tree can be laid out in the grid. Concerning the constructive end of VLSI design, suppose that T is a tree which is a subdivision of Th and is also isomorphic to a subgraph of the n×n grid graph. Define the expansion ratio of such a layout to be n2/n(Th)=n2/(2h+1−1). We show constructively that the minimum possible expansion ratio over all layouts of Th is bounded above by 1.4656 for sufficiently large h. That is, we give efficient layouts of complete binary trees into square grids, making improvements upon the previous work of others. We also give bounds for the point expansion and expansion problems for layouts of Th into extended grids, i.e. grids with added diagonals

Optimal Embedding of Complete Binary Trees into Lines and Grids

We consider several graph embedding problems which have applications in parallel and distributed computing and which have been unsolved so far. Our major result is that the complete binary tree can be embedded into the square grid of the same size with almost optimal dilation (up to a very small factor). To achieve this, we first state an embedding of the complete binary tree into the line with optimal dilation. 1 Introduction Graph embedding problems have gained importance in different areas of computer science (for a survey, cf. [MS90], [Ro88]). E.g. in the field of interconnection networks for parallel computer architectures, graph embeddings can generally be used to model the simulation of network and algorithm structures on a different network. Several types of networks have been considered, like hypercubes, shuffle-exchange networks, X-trees, binary trees, grids and lines. We will take a look at the latter ones. The importance of the tree-like structures arises from their use as..