Enhancing Power Efficient Design Techniques in Deep Submicron Era

Excessive power dissipation has been one of the major bottlenecks for design and manufacture in the past couple of decades. Power efficient design has become more and more challenging when technology scales down to the deep submicron era that features the dominance of leakage, the manufacture variation, the on-chip temperature variation and higher reliability requirements, among others. Most of the computer aided design (CAD) tools and algorithms currently used in industry were developed in the pre deep submicron era and did not consider the new features explicitly and adequately. Recent research advances in deep submicron design, such as the mechanisms of leakage, the source and characterization of manufacture variation, the cause and models of on-chip temperature variation, provide us the opportunity to incorporate these important issues in power efficient design. We explore this opportunity in this dissertation by demonstrating that significant power reduction can be achieved with only minor modification to the existing CAD tools and algorithms. First, we consider peak current, which has become critical for circuit's reliability in deep submicron design. Traditional low power design techniques focus on the reduction of average power. We propose to reduce peak current while keeping the overhead on average power as small as possible. Second, dual Vt technique and gate sizing have been used simultaneously for leakage savings. However, this approach becomes less effective in deep submicron design. We propose to use the newly developed process-induced mechanical stress to enhance its performance. Finally, in deep submicron design, the impact of on-chip temperature variation on leakage and performance becomes more and more significant. We propose a temperature-aware dual Vt approach to alleviate hot spots and achieve further leakage reduction. We also consider this leakage-temperature dependency in the dynamic voltage scaling approach and discover that a commonly accepted result is incorrect for the current technology. We conduct extensive experiments with popular design benchmarks, using the latest industry CAD tools and design libraries. The results show that our proposed enhancements are promising in power saving and are practical to solve the low power design challenges in deep submicron era

Optimal PWM switching strategy for single-phase AC-DC converters

The thesis describes an optimal selective harmonic elimination strategy suitable for singlephase AC-DC converter-fed traction drives. The objective is to eliminate low-order supply current harmonics, including those injected into the supply due to load-side current ripple. Other advantages that the switching strategy has to offer over phase-control include improved supply power factor, reduced VA consumption for a given demand speed and load, reduced torque and speed ripple and smaller armature circuit smoothing inductance. The effect of field current boost on the dynamic response of the drive is also described. It is shown that field boost helps to reduce the speed rise-time by increasing the electromagnetic torque available during acceleration periods. Closed-loop control of a 4-quadrant DC drive is described and a comparison made between the performance of PID-control and pseudo-derivative feedback control. It is shown that pseudo-derivative feedback control has several advantages to offer, amongst which are ease of tuning of the controller gains and a superior performance following load torque disturbances. A laboratory size drive system was designed and built, and used to validate simulation predictions for both the switching strategy and pseudo-derivative feedback control. A microcontroller based hardware implementation of both the switching strategy and a digital pseudo-derivative feedback controller was adopted, with the switching strategy being implemented using an off-line approach of precalculating the switching angles and storing these in look-up tables. The armature voltage controller comprises a dual-converter employing IGBTs as switching devices. The use of IGBTs allows higher switching frequencies at significant power levels than would be possible if GTOs were used. It also simplifies the gate drive circuit design and minimises the need to use snubber circuits

A Scalable Correlator Architecture Based on Modular FPGA Hardware, Reuseable Gateware, and Data Packetization

A new generation of radio telescopes is achieving unprecedented levels of sensitivity and resolution, as well as increased agility and field-of-view, by employing high-performance digital signal processing hardware to phase and correlate large numbers of antennas. The computational demands of these imaging systems scale in proportion to BMN^2, where B is the signal bandwidth, M is the number of independent beams, and N is the number of antennas. The specifications of many new arrays lead to demands in excess of tens of PetaOps per second. To meet this challenge, we have developed a general purpose correlator architecture using standard 10-Gbit Ethernet switches to pass data between flexible hardware modules containing Field Programmable Gate Array (FPGA) chips. These chips are programmed using open-source signal processing libraries we have developed to be flexible, scalable, and chip-independent. This work reduces the time and cost of implementing a wide range of signal processing systems, with correlators foremost among them,and facilitates upgrading to new generations of processing technology. We present several correlator deployments, including a 16-antenna, 200-MHz bandwidth, 4-bit, full Stokes parameter application deployed on the Precision Array for Probing the Epoch of Reionization.Comment: Accepted to Publications of the Astronomy Society of the Pacific. 31 pages. v2: corrected typo, v3: corrected Fig. 1

Power Interface Design and System Stability Analysis for 400 V DC-Powered Data Centers

The demands of high performance cloud computation and internet services have increased in recent decades. These demands have driven the expansion of existing data centers and the construction of new data centers. The high costs of data center downtime are pushing designers to provide high reliability power supplies. Thus, there are significant research questions and challenges to design efficient and environmentally friendly data centers with address increasing energy prices and distributed energy developments. This dissertation work aims to study and investigate the suitable technologies of power interface and system level configuration for high efficiency and reliable data centers. A 400 V DC-powered data center integrated with solar power and hybrid energy storage is proposed to reduce the power loss and cable cost in data centers. A cascaded totem-pole bridgeless PFC converter to convert grid ac voltage to the 400 V dc voltage is proposed in this work. Three main control strategies are developed for the power converters. First, a model predictive control is developed for the cascaded totem-pole bridgeless PFC converter. This control provides stable transient performance and high power efficiency. Second, a power loss model based dual-phase-shift control is applied for the efficiency improvement of dual-active bridge converter. Third, an optimized maximum power point tracking (MPPT) control for solar power and a hybrid energy storage unit (HESU) control are given in this research work. The HESU consists of battery and ultracapacitor packs. The ultracapacitor can improve the battery lifetime and reduce any transients affecting grid side operation. The large signal model of a typical solar power integrated datacenter is built to analyze the system stability with various conditions. The MATLAB/Simulink™-based simulations are used to identify the stable region of the data center power supply. This can help to analyze the sensitivity of the circuit parameters, which include the cable inductance, resistance, and dc bus capacitance. This work analyzes the system dynamic response under different operating conditions to determine the stability of the dc bus voltage. The system stability under different percentages of solar power and hybrid energy storage integrated in the data center are also investigated

Power Interface Design and System Stability Analysis for 400 V DC-Powered Data Centers

The demands of high performance cloud computation and internet services have increased in recent decades. These demands have driven the expansion of existing data centers and the construction of new data centers. The high costs of data center downtime are pushing designers to provide high reliability power supplies. Thus, there are significant research questions and challenges to design efficient and environmentally friendly data centers with address increasing energy prices and distributed energy developments. This dissertation work aims to study and investigate the suitable technologies of power interface and system level configuration for high efficiency and reliable data centers. A 400 V DC-powered data center integrated with solar power and hybrid energy storage is proposed to reduce the power loss and cable cost in data centers. A cascaded totem-pole bridgeless PFC converter to convert grid ac voltage to the 400 V dc voltage is proposed in this work. Three main control strategies are developed for the power converters. First, a model predictive control is developed for the cascaded totem-pole bridgeless PFC converter. This control provides stable transient performance and high power efficiency. Second, a power loss model based dual-phase-shift control is applied for the efficiency improvement of dual-active bridge converter. Third, an optimized maximum power point tracking (MPPT) control for solar power and a hybrid energy storage unit (HESU) control are given in this research work. The HESU consists of battery and ultracapacitor packs. The ultracapacitor can improve the battery lifetime and reduce any transients affecting grid side operation. The large signal model of a typical solar power integrated datacenter is built to analyze the system stability with various conditions. The MATLAB/Simulink™-based simulations are used to identify the stable region of the data center power supply. This can help to analyze the sensitivity of the circuit parameters, which include the cable inductance, resistance, and dc bus capacitance. This work analyzes the system dynamic response under different operating conditions to determine the stability of the dc bus voltage. The system stability under different percentages of solar power and hybrid energy storage integrated in the data center are also investigated

The Universe at Extreme Scale: Multi-Petaflop Sky Simulation on the BG/Q

Remarkable observational advances have established a compelling cross-validated model of the Universe. Yet, two key pillars of this model -- dark matter and dark energy -- remain mysterious. Sky surveys that map billions of galaxies to explore the `Dark Universe', demand a corresponding extreme-scale simulation capability; the HACC (Hybrid/Hardware Accelerated Cosmology Code) framework has been designed to deliver this level of performance now, and into the future. With its novel algorithmic structure, HACC allows flexible tuning across diverse architectures, including accelerated and multi-core systems. On the IBM BG/Q, HACC attains unprecedented scalable performance -- currently 13.94 PFlops at 69.2% of peak and 90% parallel efficiency on 1,572,864 cores with an equal number of MPI ranks, and a concurrency of 6.3 million. This level of performance was achieved at extreme problem sizes, including a benchmark run with more than 3.6 trillion particles, significantly larger than any cosmological simulation yet performed.Comment: 11 pages, 11 figures, final version of paper for talk presented at SC1

High performance IC clock networks with grid and tree topologies

In this dissertation, an essential step in the integrated circuit (IC) physical design flow—the clock network design—is investigated. Clock network design entailsa series of computationally intensive, large-scale design and optimization tasks for the generation and distribution of the clock signal through different topologies. The lack or inefficacy of the automation for implementing high performance clock networks, especially for low-power, high speed and variation-aware implementations, is the main driver for this research. The synthesis and optimization methods for the two most commonly used clock topologies in IC design—the grid topology and the tree topology—are primarily investigated.The clock mesh network, which uses the grid topology, has very low skew variation at the cost of high power dissipation. Two novel clock mesh network designmethodologies are proposed in this dissertation in order to reduce the power dissipation. These are the first methods known in literature that combine clock meshsynthesis with incremental register placement and clock gating for power saving purposes. The application of the proposed automation methods on the emerging resonant rotary clocking technology, which also has the grid topology, is investigated in this dissertation as well.The clock tree topology has the advantage of lower power dissipation compared to other traditional clock topologies (e.g. clock mesh, clock spine, clock tree with cross links) at the cost of increased performance degradation due to on-chip variations. A novel clock tree buffer polarity assignment flow is proposed in this dissertation in order to reduce these effects of on-chip variations on the clock tree topology. The proposed polarity assignment flow is the first work that introduces post-silicon, dynamic reconfigurability for polarity assignment, enabling clock gating for low power operation of the variation-tolerant clock tree networks.Ph.D., Electrical Engineering -- Drexel University, 201