4-Dimensional Tracking with Ultra-Fast Silicon Detectors

The evolution of particle detectors has always pushed the technological limit in order to provide enabling technologies to researchers in all fields of science. One archetypal example is the evolution of silicon detectors, from a system with a few channels 30 years ago, to the tens of millions of independent pixels currently used to track charged particles in all major particle physics experiments. Nowadays, silicon detectors are ubiquitous not only in research laboratories but in almost every high-tech apparatus, from portable phones to hospitals. In this contribution, we present a new direction in the evolution of silicon detectors for charge particle tracking, namely the inclusion of very accurate timing information. This enhancement of the present silicon detector paradigm is enabled by the inclusion of controlled low gain in the detector response, therefore increasing the detector output signal sufficiently to make timing measurement possible. After providing a short overview of the advantage of this new technology, we present the necessary conditions that need to be met for both sensor and readout electronics in order to achieve 4-dimensional tracking. In the last section we present the experimental results, demonstrating the validity of our research path.Comment: 72 pages, 3 tables, 55 figure

A Low Noise Sub-Sampling PLL in Which Divider Noise Is Eliminated and PD-CP Noise Is not multiplied by N^2

This paper presents a 2.2-GHz low jitter sub-sampling based PLL. It uses a phase-detector/charge-pump (PD/CP)that sub-samples the VCO output with the reference clock. In contrast to what happens in a classical PLL, the PD/CP noise is not multiplied by N2 in this sub-sampling PLL, resulting in a low noise contribution from the PD/CP. Moreover, no frequency divider is needed in the locked state and hence divider noise and power can be eliminated. An added frequency locked loop guarantees correct frequency locking without degenerating jitter performance when in lock. The PLL is implemented in a standard 0.18- m CMOS process. It consumes 4.2 mA from a 1.8 V supply and occupies an active area of 0.4 X 0.45 m

Jitter and phase noise in ring oscillators

A companion analysis of clock jitter and phase noise of single-ended and differential ring oscillators is presented. The impulse sensitivity functions are used to derive expressions for the jitter and phase noise of ring oscillators. The effect of the number of stages, power dissipation, frequency of oscillation, and short-channel effects on the jitter and phase noise of ring oscillators is analyzed. Jitter and phase noise due to substrate and supply noise is discussed, and the effect of symmetry on the upconversion of 1/f noise is demonstrated. Several new design insights are given for low jitter/phase-noise design. Good agreement between theory and measurements is observed

Synchroscan streak camera imaging at a 15-MeV photoinjector with emittance exchange

At the Fermilab A0 photoinjector facility, bunch-length measurements of the laser micropulse and the e-beam micropulse have been done in the past with a fast single-sweep module of the Hamamatsu C5680 streak camera with an intrinsic shot-to-shot trigger jitter of 10-20ps. We have upgraded the camera system with the synchroscan module tuned to 81.25MHz to provide synchronous summing capability with less than 1.5ps FWHM trigger jitter and a phase-locked delay box to provide phase stability of ~1ps over 10s of minutes. These steps allowed us to measure both the UV laser pulse train at 263nm and the e-beam via optical transition radiation (OTR). Due to the low electron beam energies and OTR signals, we typically summed over 50 micropulses with 0.25-1nC per micropulse. The phase-locked delay box allowed us to assess chromatic temporal effects and instigated another upgrade to an all-mirror input optics barrel. In addition, we added a slow sweep horizontal deflection plug-in unit to provide dual-sweep capability for the streak camera. We report on a series of measurements made during the commissioning of these upgrades including bunch-length and phase effects using the emittance exchange beamline and simultaneous imaging of a UV drive laser component, OTR, and the 800nm diagnostics laser.Comment: 26 p

Low-Jitter Clock Multiplication: a Comparioson between PLLs and DLLs

This paper shows that, for a given power budget, a practical phase-locked loop (PLL)-based clock multiplier generates less jitter than a delay-locked loop (DLL) equivalent. This is due to the fact that the delay cells in a PLL ring-oscillator can consume more power per cell than their counterparts in the DLL. We can show that this effect is stronger than the notorious jitter accumulation effect that occurs in the voltage-controlled oscillator (VCO) of a PLL. First, an analysis of the stochastic-output jitter of the architectures, due to the most important noise sources, is presented. Then, another important source of jitter in a DLL-based clock multiplier is treated, namely the stochastic mismatch in the delay cells which compose the DLL voltage-controlled delay line (VCDL). An analysis is presented that relates the stochastic spread of the delay of the cells to the output jitter of the clock multiplier. A circuit design technique, called impedance level scaling, is then presented which allows the designer to optimize the noise and mismatch behavior of a circuit, independently from other specifications such as speed and linearity. Applying this technique on a delay cell design yields a direct tradeoff between noise induced jitter and power usage, and between stochastic mismatch induced jitter and power usage

Noise shaping Asynchronous SAR ADC based time to digital converter

Time-to-digital converters (TDCs) are key elements for the digitization of timing information in modern mixed-signal circuits such as digital PLLs, DLLs, ADCs, and on-chip jitter-monitoring circuits. Especially, high-resolution TDCs are increasingly employed in on-chip timing tests, such as jitter and clock skew measurements, as advanced fabrication technologies allow fine on-chip time resolutions. Its main purpose is to quantize the time interval of a pulse signal or the time interval between the rising edges of two clock signals. Similarly to ADCs, the performance of TDCs are also primarily characterized by Resolution, Sampling Rate, FOM, SNDR, Dynamic Range and DNL/INL. This work proposes and demonstrates 2nd order noise shaping Asynchronous SAR ADC based TDC architecture with highest resolution of 0.25 ps among current state of art designs with respect to post-layout simulation results. This circuit is a combination of low power/High Resolution 2nd Order Noise Shaped Asynchronous SAR ADC backend with simple Time to Amplitude converter (TAC) front-end and is implemented in 40nm CMOS technology. Additionally, special emphasis is given on the discussion on various current state of art TDC architectures.Electrical and Computer Engineerin