On the effect of floorplanning on the yield of large area integrated circuits

Until recently, VLSI designers rarely considered yield issues when selecting a floorplan for a newly designed chip. This paper demonstrates that for large area VLSI chips, especially those that incorporate some fault tolerance, changes in the floorplan can affect the projected yield. We study several general floorplan structures, make some specific recommendations, and apply them to actual VLSI chips. We conclude that the floorplan of a chip can affect its projected yield in a non-negligible way, for chips with or without fault-tolerance. Index Terms -- Clustering, defects, fault-tolerant ICs, floorplan, large-area ICs, yield. 1. Introduction In the process of designing a new chip, yield issues are rarely a factor in the choice of the floorplan. This is justified when the chip is relatively small and the defect distribution can be accurately described by either the Poisson or the compound Poisson yield models ([3]). In particular, in the most commonly used compound Poisson model, i.e..