1 research outputs found
Efficient Realization of Givens Rotation through Algorithm-Architecture Co-design for Acceleration of QR Factorization
We present efficient realization of Generalized Givens Rotation (GGR) based
QR factorization that achieves 3-100x better performance in terms of
Gflops/watt over state-of-the-art realizations on multicore, and General
Purpose Graphics Processing Units (GPGPUs). GGR is an improvement over
classical Givens Rotation (GR) operation that can annihilate multiple elements
of rows and columns of an input matrix simultaneously. GGR takes 33% lesser
multiplications compared to GR. For custom implementation of GGR, we identify
macro operations in GGR and realize them on a Reconfigurable Data-path (RDP)
tightly coupled to pipeline of a Processing Element (PE). In PE, GGR attains
speed-up of 1.1x over Modified Householder Transform (MHT) presented in the
literature. For parallel realization of GGR, we use REDEFINE, a scalable
massively parallel Coarse-grained Reconfigurable Architecture, and show that
the speed-up attained is commensurate with the hardware resources in REDEFINE.
GGR also outperforms General Matrix Multiplication (gemm) by 10% in-terms of
Gflops/watt which is counter-intuitive