14,730 research outputs found
Performance and Reliability Analysis of Cross-Layer Optimizations of NAND Flash Controllers
NAND flash memories are becoming the predominant technology in the implementation of mass storage systems for both embedded and high-performance applications. However, when considering data and code storage in non-volatile memories (NVMs), such as NAND flash memories, reliability and performance be- come a serious concern for systems' designer. Designing NAND flash based systems based on worst-case scenarios leads to waste of resources in terms of performance, power consumption, and storage capacity. This is clearly in contrast with the request for run-time reconfigurability, adaptivity, and resource optimiza- tion in nowadays computing systems. There is a clear trend toward supporting differentiated access modes in flash memory controllers, each one setting a differentiated trade-off point in the performance-reliability optimization space. This is supported by the possibility of tuning the NAND flash memory performance, reli- ability and power consumption acting on several tuning knobs such as the flash programming algorithm and the flash error correcting code. However, to successfully exploit these degrees of freedom, it is mandatory to clearly understand the effect the combined tuning of these parameters have on the full NVM sub-system. This paper performs a comprehensive quantitative analysis of the benefits provided by the run-time reconfigurability of an MLC NAND flash controller through the combined effect of an adaptable memory programming circuitry coupled with run-time adaptation of the ECC correction capability. The full non- volatile memory (NVM) sub-system is taken into account, starting from the characterization of the low level circuitry to the effect of the adaptation on a wide set of realistic benchmarks in order to provide the readers a clear figure of the benefit this combined adaptation would provide at the system leve
Increasing Flash Memory Lifetime by Dynamic Voltage Allocation for Constant Mutual Information
The read channel in Flash memory systems degrades over time because the
Fowler-Nordheim tunneling used to apply charge to the floating gate eventually
compromises the integrity of the cell because of tunnel oxide degradation.
While degradation is commonly measured in the number of program/erase cycles
experienced by a cell, the degradation is proportional to the number of
electrons forced into the floating gate and later released by the erasing
process. By managing the amount of charge written to the floating gate to
maintain a constant read-channel mutual information, Flash lifetime can be
extended. This paper proposes an overall system approach based on information
theory to extend the lifetime of a flash memory device. Using the instantaneous
storage capacity of a noisy flash memory channel, our approach allocates the
read voltage of flash cell dynamically as it wears out gradually over time. A
practical estimation of the instantaneous capacity is also proposed based on
soft information via multiple reads of the memory cells.Comment: 5 pages. 5 figure
When Do WOM Codes Improve the Erasure Factor in Flash Memories?
Flash memory is a write-once medium in which reprogramming cells requires
first erasing the block that contains them. The lifetime of the flash is a
function of the number of block erasures and can be as small as several
thousands. To reduce the number of block erasures, pages, which are the
smallest write unit, are rewritten out-of-place in the memory. A Write-once
memory (WOM) code is a coding scheme which enables to write multiple times to
the block before an erasure. However, these codes come with significant rate
loss. For example, the rate for writing twice (with the same rate) is at most
0.77.
In this paper, we study WOM codes and their tradeoff between rate loss and
reduction in the number of block erasures, when pages are written uniformly at
random. First, we introduce a new measure, called erasure factor, that reflects
both the number of block erasures and the amount of data that can be written on
each block. A key point in our analysis is that this tradeoff depends upon the
specific implementation of WOM codes in the memory. We consider two systems
that use WOM codes; a conventional scheme that was commonly used, and a new
recent design that preserves the overall storage capacity. While the first
system can improve the erasure factor only when the storage rate is at most
0.6442, we show that the second scheme always improves this figure of merit.Comment: to be presented at ISIT 201
Flash-memories in Space Applications: Trends and Challenges
Nowadays space applications are provided with a processing power absolutely overcoming the one available just a few years ago. Typical mission-critical space system applications include also the issue of solid-state recorder(s). Flash-memories are nonvolatile, shock-resistant and power-economic, but in turn have different drawbacks. A solid-state recorder for space applications should satisfy many different constraints especially because of the issues related to radiations: proper countermeasures are needed, together with EDAC and testing techniques in order to improve the dependability of the whole system. Different and quite often contrasting dimensions need to be explored during the design of a flash-memory based solid- state recorder. In particular, we shall explore the most important flash-memory design dimensions and trade-offs to tackle during the design of flash-based hard disks for space application
Trade-offs between Instantaneous and Total Capacity in Multi-Cell Flash Memories
The limited endurance of ïŹash memories is a major
design concern for enterprise storage systems. We propose a
method to increase it by using relative (as opposed to ïŹxed)
cell levels and by representing the information with Write
Asymmetric Memory (WAM) codes. Overall, our new method
enables faster writes, improved reliability as well as improved
endurance by allowing multiple writes between block erasures.
We study the capacity of the new WAM codes with relative levels,
where the information is represented by multiset permutations
induced by the charge levels, and show that it achieves the
capacity of any other WAM codes with the same number of
writes. Specifically, we prove that it has the potential to double
the total capacity of the memory. Since capacity can be achieved
only with cells that have a large number of levels, we propose a
new architecture that consists of multi-cells - each an aggregation
of a number of ïŹoating gate transistors
Correcting Charge-Constrained Errors in the Rank-Modulation Scheme
We investigate error-correcting codes for a the
rank-modulation scheme with an application to flash memory
devices. In this scheme, a set of n cells stores information in the
permutation induced by the different charge levels of the individual
cells. The resulting scheme eliminates the need for discrete
cell levels, overcomes overshoot errors when programming cells (a
serious problem that reduces the writing speed), and mitigates the
problem of asymmetric errors. In this paper, we study the properties
of error-correcting codes for charge-constrained errors in the
rank-modulation scheme. In this error model the number of errors
corresponds to the minimal number of adjacent transpositions required
to change a given stored permutation to another erroneous
oneâa distance measure known as Kendallâs Ï-distance.We show
bounds on the size of such codes, and use metric-embedding techniques
to give constructions which translate a wealth of knowledge
of codes in the Lee metric to codes over permutations in Kendallâs
Ï-metric. Specifically, the one-error-correcting codes we construct
are at least half the ball-packing upper bound
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