On Nominal Delay Minimization in LUT-Based FPGA Technology Mapping

In this report, we study the LUT-based FPGA technology mapping problem for delay minimization under the nominal delay model, which assumes that the interconnect delay of a net is proportional to the fanout size of the net. First, we prove several complexity results on LUT mapping under the nominal delay model. We prove that the delay-optimal K-LUT mapping problem under the nominal delay model is NP-hard when K³3, and remain NP-hard for duplication-free mapping and tree-based mapping for K³5. Also, we show that for K=2 the delay-optimal duplication-free mapping or tree-based mapping under the nominal delay model can be solved in polynomial time. Next, we develop a heuristic LUT mapping algorithm for nominal delay minimization. Experimental results have shown that our heuristic algorithm can produce mapping solutions of smaller delay compared with the solutions of depth-optimal mapping algorithm under the unit delay model. Area of Interest: (1) Combinational Logic Synthesis. -11. Intro..

On Nominal Delay Minimization in LUT-Based FPGA Technology Mapping

We study the nominal delay minimization problem in LUTbased FPGA technology mapping, where interconnect delay is assumed proportional to net fanout size. We prove that the delay-optimal K-LUT mapping problem under the nominal delay model is NP-hard when K # 3, and remains NP-hard for duplication-free mapping and tree-based mapping for K # 5 (but is polynomial time solvable for K # 2). We also present a simple heuristic to take nominal delay into consideration during LUT mapping for delay minimization.

Abstract On Nominal Delay Minimization in LUT-Based FPGA Technology Mapping

In this report, we study the LUT-based FPGA technology mapping problem for delay minimization under the nominal delay model, which assumes that the interconnect delay of a net is proportional to the fanout size of the net. First, we prove several complexity results on LUT mapping under the nominal delay model. We prove that the delay-optimal K-LUT mapping problem under the nominal delay model is NP-hard when K!3, and remain NP-hard for duplication-free mapping and tree-based mapping for K!5. Also, we show that for K =2 the delay-optimal duplication-free mapping or tree-based mapping under the nominal delay model can be solved in polynomial time. Next, we develop a heuristic LUT mapping algorithm for nominal delay minimization. Experimental results have shown that our heuristic algorithm can produce mapping solutions of smaller delay compared with the solutions of depth-optimal mapping algorithm under the unit delay model. Area of Interest: (1) Combinational Logic Synthesis