1 research outputs found
Addressing Resiliency of In-Memory Floating Point Computation
In-memory computing (IMC) can eliminate the data movement between processor
and memory which is a barrier to the energy-efficiency and performance in
Von-Neumann computing. Resistive RAM (RRAM) is one of the promising devices for
IMC applications (e.g. integer and Floating Point (FP) operations and random
logic implementation) due to low power consumption, fast operation, and small
footprint in crossbar architecture. In this paper, we propose FAME, a pipelined
FP arithmetic (adder/subtractor) using RRAM crossbar based IMC. A novel shift
circuitry is proposed to lower the shift overhead during FP operations. Since
96% of the RRAMs used in our architecture are in High Resistance State (HRS),
we propose two approaches namely Shift-At-The-Output (SATO) and Force To VDD
(FTV) (ground (FTG)) to mitigate Stuck-at-1 (SA1) failures. In both techniques,
the fault-free RRAMs are exploited to perform the computation by using an extra
clock cycle. Although performance degrades by 50%, SATO can handle 50% of the
faults whereas FTV can handle 99% of the faults in the RRAM-based compute array
at low power and area overhead. Simulation results show that the proposed
single precision FP adder consumes 335 pJ and 322 pJ for NAND-NAND and NOR-NOR
based implementations, respectively. The area overheads of SATO and FTV are
28.5% and 9.5%, respectively