Reversible Logic Synthesis of Fault Tolerant Carry Skip BCD Adder

Reversible logic is emerging as an important research area having its application in diverse fields such as low power CMOS design, digital signal processing, cryptography, quantum computing and optical information processing. This paper presents a new 4*4 parity preserving reversible logic gate, IG. The proposed parity preserving reversible gate can be used to synthesize any arbitrary Boolean function. It allows any fault that affects no more than a single signal readily detectable at the circuit's primary outputs. It is shown that a fault tolerant reversible full adder circuit can be realized using only two IGs. The proposed fault tolerant full adder (FTFA) is used to design other arithmetic logic circuits for which it is used as the fundamental building block. It has also been demonstrated that the proposed design offers less hardware complexity and is efficient in terms of gate count, garbage outputs and constant inputs than the existing counterparts.Comment: 9 pages, 7 figures, 5 table

Quantum Cost Optimization for Reversible Carry Skip BCD Adder

Reversible Logic is a very promising and flourishing research area. Reversible logic theoretically allows designers to build subsystem circuit design with zero power dissipation than the existing classical ones. However synthesis of reversible circuit is not easy. In this paper we propose an efficient approach for carry skip BCD adder using reversible logic. Our results show that our design is much more efficient than the existing ones in terms quantum cost, garbage outputs and delay

Quantum cost efficient reversible . . .

Reversible logic allows low power dissipating circuit design and founds its application in cryptography, digital signal processing, quantum and optical information processing. This paper presents a novel quantum cost efficient reversible BCD adder for nanotechnology based systems using PFAG gate. It has been demonstrated that the proposed design offers less hardware complexity and requires minimum number of garbage outputs than the existing counterparts. The remarkable property of the proposed designs is that its quantum realization is given in NMR technology

STRUCTURING REVERSIBLE CIRCUIT TO OVERCOME LOW-POWER DISSIPATION

This paper presents a design methodology for that realization of Booth’s multiplier in reversible mode. Booth’s multiplier is recognized as among the fastest multipliers in literature so we have proven a competent design methodology in reversible paradigm. Reversible logic attains the attraction of researchers within the last decade mainly because of low-power dissipation. Designers’ endeavors therefore are ongoing in creating complete reversible circuits composed of reversible gates. All of the theorems provide lower bounds for quantity of gates, garbage outputs, circuit delay and quantum cost. The important thing achievement from the design is, it is capable of doing dealing with both signed and unsigned figures, which isn't contained in the present circuits considered within this paper. We assess the 4×4 form of the suggested Booth’s multiplier using the two existing designs. Theoretical underpinnings, established for that suggested design, reveal that the suggested circuit is extremely efficient from reversible circuit design perspective. The suggested architecture is capable of doing performing both signed and unsigned multiplication of two operands without getting any feedbacks, whereas existing multipliers in reversible mode consider loop that is strictly disallowed reversible logic design