XNOR-VSH: A Valley-Spin Hall Effect-based Compact and Energy-Efficient Synaptic Crossbar Array for Binary Neural Networks

Binary neural networks (BNNs) have shown an immense promise for resource-constrained edge artificial intelligence (AI) platforms as their binarized weights and inputs can significantly reduce the compute, storage and communication costs. Several works have explored XNOR-based BNNs using SRAMs and nonvolatile memories (NVMs). However, these designs typically need two bit-cells to encode signed weights leading to an area overhead. In this paper, we address this issue by proposing a compact and low power in-memory computing (IMC) of XNOR-based dot products featuring signed weight encoding in a single bit-cell. Our approach utilizes valley-spin Hall (VSH) effect in monolayer tungsten di-selenide to design an XNOR bit-cell (named 'XNOR-VSH') with differential storage and access-transistor-less topology. We co-optimize the proposed VSH device and a memory array to enable robust in-memory dot product computations between signed binary inputs and signed binary weights with sense margin (SM) > 1 micro-amps. Our results show that the proposed XNOR-VSH array achieves 4.8% ~ 9.0% and 37% ~ 63% lower IMC latency and energy, respectively, with 4 % ~ 64% smaller area compared to spin-transfer-torque (STT)-MRAM and spin-orbit-torque (SOT)-MRAM based XNOR-arrays

The Fourth Element: Characteristics, Modelling, and Electromagnetic Theory of the Memristor

In 2008, researchers at HP Labs published a paper in {\it Nature} reporting the realisation of a new basic circuit element that completes the missing link between charge and flux-linkage, which was postulated by Leon Chua in 1971. The HP memristor is based on a nanometer scale TiO$_2$ thin-film, containing a doped region and an undoped region. Further to proposed applications of memristors in artificial biological systems and nonvolatile RAM (NVRAM), they also enable reconfigurable nanoelectronics. Moreover, memristors provide new paradigms in application specific integrated circuits (ASICs) and field programmable gate arrays (FPGAs). A significant reduction in area with an unprecedented memory capacity and device density are the potential advantages of memristors for Integrated Circuits (ICs). This work reviews the memristor and provides mathematical and SPICE models for memristors. Insight into the memristor device is given via recalling the quasi-static expansion of Maxwell's equations. We also review Chua's arguments based on electromagnetic theory.Comment: 28 pages, 14 figures, Accepted as a regular paper - the Proceedings of Royal Society